NXP Semiconductors MPC5644A, Reference Manual, Page: 888 / 1735

Enhanced Time Processing Unit (eTPU2)
MPC5644A Microcontroller Reference Manual, Rev. 6
888 Freescale Semiconductor
• Angle Clock Mode: Count internal tooth angle in combination with the eTPU Angle Counter
(EAC) hardware which implements an Angle PLL, and generates angle information to the
channels. This mode is targeted for angle based applications.
• STAC (STAC) Bus Client Mode: TCR2 is driven by an external source (see Section 24.5.6.2.4,
STAC bus client mode ).
• Gated Mode: Count with rate derived from the system clock divided by eight. The TCRCLK signal
is used to gate this count, enabling pulse accumulator operations.
• Internally Clocked Modes: TCR2 is driven by internal clock, with count rate either system clock
divided by eight or driven from the rising edge of a Peripheral Timebase Clock defined at MCU
integration. The use and rate of the Peripheral Timebase Clock is MCU-dependent, but must not
exceed system clock divided by two.
All clock sources pass through a prescaler. In addition, the TCR2 count can be originated from the EAC
which is a hardware angle clock and angle counter.
Figure 24-50 shows the diagram for TCR2 clock
control. When TCR2 is not driven by the EAC or STAC, the ETPU_TBCR field TCR2CTL selects the
clock source, also allowing TCR2 to be frozen independently of TCR1 (see
Section 24.4.3.1,
ETPU_TBCR – eTPU Time Base Configuration Register ). When in Angle Mode, TCR2CTL selects the
TCRCLK edge sensitivity.
Figure 24-50. TCR2 Clock Control
The TCRCLK signal input is passed through a synchronizer and a programmable digital filter. In Angle
Mode with AM = 01, synchronizer and filter are also used in Channel 0, replacing its input synchronizer
and filter, to get the same timing in the EAC and Channel 0. The TCRCLK synchronizer is an improved
filter that provides best latency while maintaining proper noise filtering (see
Section 24.4.3.1,
ETPU_TBCR – eTPU Time Base Configuration Register , field TCRCF[1:0]—TCRCLK Signal Filter
Control).
SYNC.
SYSTEM CLK / 8
ETPU_TBCR
TCR2
0 23
TCR2
PRESC.
TCRCLK
PROGRAMMABLE
DIGITAL
FILTER
ETPU_TBCR
000
001
010
011
1, 2, . . . , 64
FILTER
CLOCK
SYSTEM
CLOCK/2
0
1
6
2 samp
Integr.
3
ETPU_ECR[FPSCK]
ETPU_TBCR[TCRCF1]
GEN.
FILTER CLOCK
eTPU ANGLE
Angle Mode
ETPU_TBCR[AM]
1
0
COUNTER
Pin
[TCR2CTL]
3
[TCR2P]
(EAC)
to Channel 0 input on Angle Mode (AM = 01)
101
PERIPHERAL TIMEBASE
CLOCK
Filtered signal for TCR1 clock
ETPU_TBCR[TCRCF0]
1 0
to all channel filter
clocks
111
no clock
100
STAC bus