NXP Semiconductors MPC5644A, Reference Manual, Page: 752 / 1735

Enhanced Time Processing Unit (eTPU2)
MPC5644A Microcontroller Reference Manual, Rev. 6
752 Freescale Semiconductor
on channel number and assigned priority. The priority mechanism, implemented in hardware, ensures that
all requesting channels are serviced. For additional details refer to
Section 24.5.3, Scheduler .
24.2.1.1.6 Microengine
eTPU microengine is a simple VLIW implementation that performs each instruction in a microcycle of
two system clocks, while prefetching the next instruction through an instruction pipeline. Instruction
execution time is constant unless it gets wait states from the SPRAM arbitration. Two eTPU engines share
code memory without having any performance degradation by interleaving their accesses (the Shared
Code Memory has one-clock access time).
Instruction width is 32 bits. The microengine instruction set provides basic arithmetic and logic operations,
flow control (jumps and subroutine calls), SPRAM access, and Channel configuration and control. The
instruction formats are defined in such a way that allow particular combinations of two or three of these
operations with unconflicting resources to be executed in parallel in the same microcycle.
Microengine has also an independent Multiply/Divide/MAC unit that performs these complex operations
in parallel with other microengine instructions.
Channel functionality is tightly integrated to the instruction set through Channel Control operations and
conditional Branch operations, which support jumps/calls on Channel-specific conditions. This allows
quick and terse Channel configuration and control code, contributing to reduced service time.
Detailed description can be found in Section 24.5.8, Microengine .
24.2.1.1.7 Single vs. dual eTPU engine system
An eTPU implementation can include one or two eTPU engines. The number is engines is specific to the
microcontroller design and cannot be changed.
NOTE
The MPC5644A eTPU has one eTPU2 engine.
On devices with two eTPU engines, the eTPU parameter RAM (SPRAM), code memory (SCM) and Bus
Interface Unit (BIU) are shared by both engines, enabling processor core-to-eTPU communication and
eTPU engine-to-engine communication.
In dual-engine eTPUs the shared BIU includes coherency logic which supports dual-parameter (8 bytes)
coherency in transfers between the processor core and eTPU, using a temporary parameter area within the
SPRAM. More details on this can be found on
Section 24.5.4, Parameter sharing and coherency .
24.2.2 Features
24.2.2.1 eTPU feature summary
The eTPU includes these distinctive features:
• Up to 32 channels per eTPU engine—each channel is associated with an I/O signal pair.
— Enhanced input digital filters on the input pins for improved noise immunity. The eTPU digital
filter can use 2 samples, 3 samples or work in continuous mode.