NXP Semiconductors MPC5644A, Reference Manual, Page: 912 / 1735

Enhanced Time Processing Unit (eTPU2)
MPC5644A Microcontroller Reference Manual, Rev. 6
912 Freescale Semiconductor
is written fist and TICKS on the second microinstruction after (for instance with a NOP between them),
making the new TICKS value valid for the next tooth regardless of the mode.
The mode-dependent behavior is:
• In Normal mode, the new TICKS value becomes valid before EAC goes High Rate due to the IPH;
• In Halt mode, the EAC goes to Normal mode, and new TICKS is valid for the next tooth;
• In High Rate mode, the new TICKS value is effective when EAC leaves High Rate mode, and IPH
is ignored;
24.5.7.12.4 IPH and MISSCNT
If both IPH and MISSCNT are written non-zero values:
• In Normal mode, at the next microcycle the EAC goes to High Rate mode, the MISSCNT field in
TPR goes to 0, and the missing teeth are counted in High Rate mode.
• In Halt mode, the EAC goes to Normal mode for one microcycle and then, yet another microcycle
later, goes to High Rate mode, counting the missing teeth. The TPR fields IPH and MISSCNT are
zeroed on the transition from Normal to High Rate mode.
• In High Rate mode, IPH is ignored (resetting at the next microcycle) and MISSCNT is buffered
(see
Section 24.5.7.12.1, TPR buffering ).
24.5.7.12.5 IPH and HOLD
If IPH and HOLD are asserted at once, IPH cancels the HOLD and both reset. The EAC is not frozen,
regardless of the mode.
24.5.7.12.6 LAST and HOLD
If LAST and HOLD are written 1 at once, LAST asserts and EAC is frozen. When a physical tooth is
detected or IPH is asserted, the EAC is unfrozen in the same state it was before, and LAST is kept asserted.
24.5.8 Microengine
Each eTPU engine has a microengine that fetches, decodes and executes microinstructions. The
Microengine only works when there are service requests to be attended, otherwise it turns to idle state,
controlled by Hardware Scheduler (see
Section 24.5.3, Scheduler ).
Microcode is stored in Shared Code Memory (SCM) that is 32-bit wide. Microengine can access SPRAM
using a different bus from the one used to accesses code memory, so that code and data can be accessed at
the same time (Harvard Architecture).
Some of eTPU functionality can only be made through the microengine, like configuring channels and
interrupting host. Microengine gives eTPU a high degree of flexibility, since any desired treatment for
channel’s events can be implemented; however, that flexibility comes at the cost of channel service’s
latency. Latency is worsened when channels from a same eTPU engine contend for microengine service.
In
Figure 24-62 a block diagram of microengine architecture is shown.
Microengine features are summarized as follows: