NXP Semiconductors MPC5644A, Reference Manual, Page: 691 / 1735

Reaction Module (REACM)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 691
• If the FREN bit is asserted and a global debug signal is issued the module enters debug mode.
In debug mode, the channel outputs are held at HOD (High Output Drive), LOD (Low Output Drive), or
Drive Off (DOFF) state, as determined by the current channel state. When resuming normal operation after
exiting debug mode the channel output is set to DOFF until the next timer control rising edge occurs.
The ADC Maximum Limit Detection (REACM_CHSRn[MAXL]) flag is the only flag that operates in
debug mode. All other flags keep the state present when the module entered debug mode. Note that the
corresponding error flag in the REACM Global Error Flag Register (REACM_GEFR) (
Figure 23-8 ) is
also set.
The REACM ADC Sensor Input Register (REACM_SINR) allows direct access for write to the TAG and
ADC result values input to the reaction module. This software control may be used for module debug
purposes. Please see
Figure 23-7 .
23.1.3 Block diagram
Figure 23-1 shows the on-chip connections of the reaction module. The ADC module is the source of data
monitored from external sensors, usually voltage information, which is used by the reaction channel
modulation to generate an PWM signal control signal in order to maintain the load current within a certain
predefined boundary. The on-chip eTPU module is commonly used as the source for controlling the
activation of a reaction channel. Alternatively an eMIOS or PIT module can be used to provide that control
signal.
Figure 23-1. Reaction module system interconnection
eTPU
eTPU
Reaction Module
CPU
register access
bus
(eTPU
channels)
device pins
ADC
side
port
ADC sampled
data
Reaction
Channels
rchn_a
rchn_b
rchn_c
System
SDM
(PSI)
can be driven by
CPU
Timer
channels