NXP Semiconductors MPC5644A, Reference Manual, Page: 564 / 1735

Frequency-modulated phase locked loop (FMPLL)
MPC5644A Microcontroller Reference Manual, Rev. 6
564 Freescale Semiconductor
17.4.2 Register descriptions
This section contains the register descriptions in ascending address order. Two different programming
models are selectable through FMPLL_ESYNCR1[EMODE]:
• Legacy model—The FMPLL is controlled by the Synthesizer Control Register (SYNCR). In this
model, the FMPLL operating mode changes automatically to normal mode when the register is
written in the first time. There is no way to switch back to bypass mode once the operating mode
has switched to normal.
• Enhanced model—The PLL is controlled by the Enhanced Synthesizer Control Registers 1–2
(ESYNCR1/ESYNCR2). In this model, it is possible to change the FMPLL operating mode back
and forth between bypass and normal modes by programming FMPLL_ESYNCR1[CLKCFG].
The reset value of FMPLL_ESYNCR1[EMODE] is determined by the SoC integration. This bit is write
once. After it is set to ‘1’, further write attempts to this bit will have no effect.
17.4.2.1 Synthesizer Control Register (SYNCR)
This register is provided for backwards compatibility with previous devices. New applications should use
ESYNCR1/ESYNCR2 instead of SYNCR.
Table 17-5. FMPLL memory map
Offset Register Location
0x0000 Synthesizer Control Register (SYNCR) on page 17-564
0x0004 Synthesizer Status Register (SYNSR) on page 17-567
0x0008 Enhanced Synthesizer Control Register 1 (ESYNCR1) on page 17-569
0x000C Enhanced Synthesizer Control Register 2 (ESYNCR2) on page 17-571
0x0010 Reserved —
0x0014 Reserved —
0x0018 Synthesizer FM Modulation Register (SYNFMMR) on page 17-572