NXP Semiconductors MPC5644A, Reference Manual, Page: 569 / 1735

Frequency-modulated phase locked loop (FMPLL)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 569
17.4.2.3 Enhanced Synthesizer Control Register 1 (ESYNCR1)
Figure 17-4. Enhanced Synthesizer Control Register 1 (ESYNCR1)
29
LOCF
Loss-of-clock flag
This bit provides the interrupt request flag for the loss-of-clock. To clear the flag, software must write a 1
to the bit. Writing 0 has no effect. This flag bit is sticky in the sense that if clocks return to normal, the bit
will remain set until cleared by either writing 1 or asserting reset. The LOCF flag is not asserted while the
FMPLL is in bypass mode. See
Section 17.5.4, Loss-of-clock detection , for information on which operating
modes and conditions can this flag be asserted.
0 No loss of clock detected. Interrupt service not requested.
1 Loss of clock detected. Interrupt service requested.
30–31 Reserved, should be cleared.
Offset 0x0008 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
EMODE
CLKCFG
0 0 0 0 0 0 0 0
EPREDIV
W
Reset 0 0 1 –
1
1
Reset value determined by the PLLREF pin.
0 0 0 0 0 0 0 0 1 1 1 1
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0
EMFD
W
Reset 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
Table 17-7. SYNSR field descriptions (continued)
Field Description