NXP Semiconductors MPC5644A, Reference Manual, Page: 1535 / 1735

FlexRay Communication Controller (FlexRay)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1535
SADR_MBHF = (FR_RSBIR[RSBIDX] * 10) + SMBA Eqn. 33-3
The length required for the message buffer data field depends on the message buffer segment that the
receive shadow buffer is assigned to. For the receive shadow buffers assigned to the first message buffer
segment, the length must be the same as for the individual message buffers assigned to the first message
buffer segment. For the receive shadow buffers assigned to the second message buffer segment, the length
must be the same as for the individual message buffers assigned to the second message buffer segment.
The receive shadow buffer assignment is described in
Receive Shadow Buffer Index Register
(FR_RSBIR) .
Figure 33-115. Receive shadow buffer structure
33.6.3.3 Receive FIFO
The receive FIFO implements a frame reception system based on the FIFO concept. The CC provides two
independent receive FIFOs, one per channel.
A receive FIFO consists of a set of physical message buffers in the FlexRay memory area and a set of
receive FIFO control registers located in dedicated registers. The structure of a receive FIFO is given in
Figure 33-116 .
The connection between the receive FIFO control registers and the set of physical message buffers is
established by the
Receive FIFO Start Index Register (FR_RFSIR) , the Receive FIFO Depth and Size
Register (RFDSR) , and the Receive FIFO A Read Index Register (FR_RFARIR) / Receive FIFO B Read
Index Register (FR_RFBRIR) . The system memory base address SMBA is defined by the system memory
base address register selected by the FIFO address mode bit FR_MCR[FAM].
The start byte address SADR_MBHF[1] of the first message buffer header field that belongs to the receive
FIFO in the FlexRay memory area is determined according to
Equation 33-4 .
SADR_MBHF[1] = (10 * FR_RFSIR[SIDX]) + SMBA Eqn. 33-4
FR_RSBIDX[3]
FR_RSBIDX[2]
FR_RSBIDX[1]
FR_RSBIDX[0]
Receive Shadow Buffer Control Registers
(min) FR_MBDSR[MBSEG1DS] * 2 bytes / FR_MBDSR[MBSEG2DS] * 2 bytes
Data Field Offset
Frame Data
Message Buffer Header Field
Message Buffer Data Field
Slot Status Frame Header
SADR_MBDF
SADR_MBHF
FlexRay Memory