NXP Semiconductors MPC5644A, Reference Manual, Page: 1502 / 1735

FlexRay Communication Controller (FlexRay)
MPC5644A Microcontroller Reference Manual, Rev. 6
1502 Freescale Semiconductor
33.5.2.49 Slot Status Counter Registers (FR_SSCR0–FR_SSCR3)
Each of these four registers provides the slot status counter value for the previous communication cycle(s)
and is updated at the cycle start. The provided value depends on the control bits and fields in the related
internal slot status counter condition register FR_SSCCRn, which can be programmed by using the
Slot
Status Counter Condition Register (FR_SSCCR) . For more details, see Section 33.6.18.4, Slot status
counter registers ”.
NOTE
If the counter has reached its maximum value 0xFFFF and is in the
multicycle mode, that is, FR_SSCCRn[MCY] = 1, the counter is not reset
to 0x0000. The application can reset the counter by clearing the
FR_SSCCRn[MCY] bit and waiting for the next cycle start, when the CC
clears the counter. Subsequently, the counter can be set into the multicycle
mode again.
33.5.2.50 MTS A Configuration Register (FR_MTSACFR)
This register controls the transmission of the Media Access Test Symbol MTS on channel A. For more
details, see
Section 33.6.13, MTS generation ”.
Base + 0x0078 (FR_SSCR0)
Base + 0x007A (FR_SSCR1)
Base + 0x007C (FR_SSCR2)
Base + 0x007E (FR_SSCR3) Additional Reset: RUN Command
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R SLOTSTATUSCNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 33-49. Slot Status Counter Registers (FR_SSCR0–FR_SSCR3)
Table 33-57. FR_SSCR0–FR_SSCR3 field description
Field Description
SLOTSTATUSCNT Slot Status Counter — This field provides the current value of the Slot Status Counter.
Base + 0x0080 Write: MTE: Anytime
CYCCNTMSK,CYCCNTVAL: POC:config
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
MTE
0
CYCCNTMSK
0 0
CYCCNTVAL
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 33-50. MTS A Configuration Register (FR_MTSACFR)