FlexRay Communication Controller (FlexRay)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
1593
After reading all the data from the locked tables, the application must unlock the table by writing to the
even table lock trigger FR_SFTCCSR[ELKT] again. The even table lock status bit FR_SFTCCSR[ELKS]
is reset immediately.
If the sync frame table generation is disabled, the table valid bits FR_SFTCCSR[EVAL] and
FR_SFTCCSR[EVAL] are reset when the counter values in the
are updated. This is done because the tables stored in the FlexRay memory area are no
longer related to the values in the
Sync Frame Counter Register (FR_SFCNTR)
.
Figure 33-155. Sync frame table trigger and generation timing
33.6.12.5 Sync frame table access
The sync frame tables will be transferred into the FlexRay memory area during the table write windows
shown in
. During the table write, the application can not lock the table that is currently
written. If the application locks the table outside of the table write window, the lock is granted
immediately.
33.6.12.5.1
Sync frame table locking and unlocking
The application locks the even/odd sync frame table by writing 1 to the lock trigger bit ELKT/OLKT in
the
Sync Frame Table Configuration, Control, Status Register (FR_SFTCCSR)
. If the affected table is not
currently written to the FlexRay memory area, the lock is granted immediately, and the lock status bit
ELKS/OLKS is set. If the affected table is currently written to the FlexRay memory area, the lock is not
granted. In this case, the application must issue the lock request again until the lock is granted.
The application unlocks the even/odd sync frame table by writing 1 to the lock trigger bit ELKT/OLKT.
The lock status bit ELKS/OLKS is cleared immediately.
33.6.13 MTS generation
The CC provides a flexible means to request the transmission of the Media Access Test Symbol MTS in
the symbol window on channel A or channel B.
The application can configure the set of communication cycles in which the MTS will be transmitted over
the FlexRay bus by programming the CYCCNTMSK and CYCCNTVAL fields in the
Configuration Register (FR_MTSACFR)
MTS B Configuration Register (MTSBCFR)
The application enables or disables the generation of the MTS on either channel by setting or clearing the
MTE control bit in the
MTS A Configuration Register (FR_MTSACFR)
. If an MTS is to be transmitted in a certain communication cycle, the application must set
the MTE control bit during the static segment of the preceding communication cycle.
FR_SFTCCSR.[OPT,SIDEN,SDVEN] write window
even table write
static segment
NIT
static segment
NIT
static segment
NIT
cycle 2n-1
cycle 2n
cycle 2n+1
odd table write
Summary of Contents for MPC5644A
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