FlexCAN Module
MPC5644A Microcontroller Reference Manual, Rev. 6
1426
Freescale Semiconductor
FlexCAN also supports an alternate masking scheme with only three mask registers (RGXMASK,
RX14MASK and RX15MASK) for backwards compatibility. This alternate masking scheme is enabled
when MCR[MBFEN] is negated.
32.5.6
Data coherence
In order to maintain data coherency and FlexCAN proper operation, the CPU must obey the rules described
in
Section 32.5.2, Transmit process
Section 32.5.4, Receive process
message buffer structure within FlexCAN other than those specified may cause FlexCAN to behave in an
unpredictable way.
32.5.6.1
Transmission abort mechanism
The abort mechanism provides a safe way to request the abortion of a pending transmission. A feedback
mechanism is provided to inform the CPU if the transmission was aborted or if the frame could not be
aborted and was transmitted instead. In order to maintain backwards compatibility, the abort mechanism
must be explicitly enabled by asserting MCR[AEN].
In order to abort a transmission, the CPU must write a specific abort code (1001) to the Code field of the
Control and Status word. When the abort mechanism is enabled, the active message buffers configured as
transmission must be aborted first and then they may be updated. If the abort code is written to a message
buffer that is currently being transmitted, or to a message buffer that was already loaded into the SMB for
transmission, the write operation is blocked and the message buffer is not deactivated, but the abort request
is captured and kept pending until one of the following conditions are satisfied:
•
The module loses the bus arbitration
•
There is an error during the transmission
•
The module is put into Freeze Mode
If none of conditions above are reached, the message buffer is transmitted correctly, the interrupt flag is
set in the corresponding IFRL or IFRH register and an interrupt to the CPU is generated (if enabled). The
abort request is automatically cleared when the interrupt flag is set. In the other hand, if one of the above
conditions is reached, the frame is not transmitted, therefore the abort code is written into the Code field,
the interrupt flag is set in the corresponding IFRL or IFRH register and an interrupt is (optionally)
generated to the CPU.
If the CPU writes the abort code before the transmission begins internally, then the write operation is not
blocked, therefore the message buffer is updated and no interrupt flag is set. In this way the CPU just needs
to read the abort code to make sure the active message buffer was deactivated. Although the AEN bit is
asserted and the CPU wrote the abort code, in this case the message buffer is deactivated and not aborted,
because the transmission did not start yet. One message buffer is only aborted when the abort request is
captured and kept pending until one of the previous conditions are satisfied.
The abort procedure can be summarized as follows:
•
CPU writes 1001 into the code field of the C/S word
•
CPU reads the CODE field and compares it to the value that was written
Summary of Contents for MPC5644A
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