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FlexCAN Module
MPC5644A Microcontroller Reference Manual, Rev. 6
1422
Freescale Semiconductor
32.5.2
Transmit process
In order to transmit a CAN frame, the CPU must prepare a Message Buffer for transmission by executing
the following procedure:
•
If the message buffer is active (transmission pending), write ‘1000’ to the Code field to inactivate
the message buffer.The deactivated message buffer can transmit without setting IFLAG and
without updating the CODE field (see
Section 32.5.6.2, Message buffer deactivation
).
•
Write the ID word.
•
Write the data bytes.
•
Write the Length, Control and Code fields of the Control and Status word to activate the message
buffer.
Once the message buffer is activated in the fourth step, it will participate into the arbitration process and
eventually be transmitted according to its priority. At the end of the successful transmission, the value of
the Free Running Timer is written into the Time Stamp field, the Code field in the Control and Status word
is updated, a status flag is set in the Interrupt Flag Register and an interrupt is generated if allowed by the
corresponding Interrupt Mask Register bit. The new Code field after transmission depends on the code that
was used to activate the message buffer in step four (see
and
). When the Abort feature is enabled (MCR[AEN] is asserted), after the Interrupt
Flag is asserted for a message buffer configured as transmit buffer, the message buffer is blocked, therefore
the CPU is not able to update it until the Interrupt Flag be negated by CPU. It means that the CPU must
clear the corresponding IFRL or IFRH register before starting to prepare this message buffer for a new
transmission or reception.
32.5.3
Arbitration process
The arbitration process is an algorithm executed by the MBM that scans the whole message buffer memory
looking for the highest priority message to be transmitted. All message buffers programmed as transmit
buffers will be scanned to find the lowest ID
1
or the lowest MB number or the highest priority, depending
on bits CR[LBUF] and MCR[LPRIO_EN]. The arbitration process is triggered in the following events:
•
During the CRC field of the CAN frame
•
During the error delimiter field of the CAN frame
•
During Intermission, if the winner message buffer defined in a previous arbitration was
deactivated, or if there was no message buffer to transmit, but the CPU wrote to the C/S word of
any message buffer after the previous arbitration finished
•
When MBM is in Idle or Bus Off state and the CPU writes to the C/S word of any message buffer
•
Upon leaving Freeze Mode
When CR[LBUF] is asserted, MCR[LPRIO_EN] has no effect and the lowest number buffer is transmitted
first. When CR[LBUF] and MCR[LPRIO_EN] are both negated, the message buffer with the lowest ID is
transmitted first but if CR[LBUF] is negated and MCR[LPRIO_EN] is asserted, the PRIO bits augment
the ID used during the arbitration process. With this extended ID concept, arbitration is done based on the
full 32-bit ID and the PRIO bits define which message buffer should be transmitted first, therefore message
1.
Actually, if CR[LBUF] is negated, the arbitration considers not only the ID, but also the RTR and IDE bits placed inside the
ID at the same positions they are transmitted in the CAN frame.
Summary of Contents for MPC5644A
Page 2: ...MPC5644A Microcontroller Reference Manual Rev 6 2 Freescale Semiconductor...
Page 24: ...MPC5644A Microcontroller Reference Manual Rev 6 24 Freescale Semiconductor...
Page 26: ...MPC5644A Microcontroller Reference Manual Rev 6 26 Freescale Semiconductor...
Page 52: ...Introduction MPC5644A Microcontroller Reference Manual Rev 6 52 Freescale Semiconductor...
Page 56: ...Memory Map MPC5644A Microcontroller Reference Manual Rev 6 56 Freescale Semiconductor...
Page 1228: ...Decimation Filter MPC5644A Microcontroller Reference Manual Rev 6 1228 Freescale Semiconductor...
Page 1440: ...FlexCAN Module MPC5644A Microcontroller Reference Manual Rev 6 1440 Freescale Semiconductor...