NXP Semiconductors MPC5644A, Reference Manual, Page: 1260 / 1735

Deserial Serial Peripheral Interface (DSPI)
MPC5644A Microcontroller Reference Manual, Rev. 6
1260 Freescale Semiconductor
30.8.2 Register descriptions
30.8.2.1 DSPI Module Configuration Register (DSPI_MCR)
The DSPI_MCR contains bits which configure various attributes associated with DSPI operation. The
HALT and MDIS bits can be changed at any time, but only take effect on the next frame boundary. Only
the HALT and MDIS bits in the DSPI_MCR are allowed to be changed, while the DSPI is in the Running
state.
DS0xD8 DSPI DSI Parallel Input Select Register 0 (DPSI_PISR0)
1
on page
30-1285
DS0xDC DSPI DSI Parallel Input Select Register 1 (DPSI_PISR1)
1
on page
30-1285
DS0xE0 DSPI DSI Parallel Input Select Register 2 (DPSI_PISR2)
1
on page
30-1285
DS0xE4 DSPI DSI Parallel Input Select Register 3 (DPSI_PISR3)
1
on page
30-1285
DS0xE8 DSPI DSI Deserialized Data Interrupt Mask Register (DSPI_DIMR) on page
30-1288
DS0xEC DSPI DSI Deserialized Data Polarity Interrupt Register (DSPI_DPIR) on page
30-1289
1
DSPI_PISR0-3 registers and assosiated with them functionality may be not implemented in particular DSPI
instances of the SOC.
Address: DSPI_BASE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
MSTR
CONT_SCKE
DCONF FRZ
MTFE
PCSSE
ROOE
PC
SI
S
7
PC
SI
S
6
PC
SI
S
5
PC
SI
S
4
PC
SI
S
3
PC
SI
S
2
PC
SI
S
1
PC
SI
S
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0
MDIS
DIS_TXF DIS_
RXF
0 0
SMPL_PT
0 0 0 0 0 0
PES HALT
W
CLR
_
TXF
CLR_R
X
F
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Figure 30-5. DSPI Module Configuration Register (DSPI_MCR)
Table 30-3. Memory map (continued)
Address Register name Location