NXP Semiconductors MPC5644A, Reference Manual, Page: 1285 / 1735

Deserial Serial Peripheral Interface (DSPI)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1285
30.8.2.18 DSPI DSI Parallel Input Select Registers 0 - 3 (DPSI_PISR0 - DPSI_PISR3)
DSPI DSI Parallel Input Select Registers 0 - 3 provide means to select each data bit for transmitted frame
from 16 Parallel Input pins. Each Input Pin Select (IPS) field controls one bit in the transmitted frame.
Each register contains control fields for 8 bits in the frame. The select field value is defined as 4 bits signed
integer number. Selected Parallel Input pin number is defined as a the field number and field value.
For example, if IPS16 is equal binary number 1111 (minus 1 decimal) bit 16 in the frame will be taken
from Parallel Input pin number . When the IPS0 is equal -1, the bit 0 in the frame is taken from Parallel
Input . When the IPS0 is equal +1, the bit 0 in the frame is taken from Parallel Input and etc.
Please, note that the DSPI_PISR0-3 only preselect Parallel Input pins, final selection to the transmitted
frame is done by DSPI_SSR register bits or DSPI_DSICR[TXSS] bit.
Address: DSP 0xD4 Access:
R
SS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R
SS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 30-23. DSPI DSI Serialization Source Select Register (DSPI_SSR)
Table 30-25. DSPI_SSR Field Descriptions
Field Description
SS[]
Source Select. The SS bits select serialization source for DSI frame. Each SS bit selects data for
corresponded bit in the transmitted frame.
0 the bit in transmitted frame is taken from Parallel Input pin;
1 the bit in transmitted frame is taken from DSPI_ASDR register
Address: DSP 0xD8 Access:
R
IPS IPS IPS IPS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R
IPS IPS IPS IPS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 30-24. DSPI DSI Parallel Input Select Register 0 (DSPI_PISR0)