NXP Semiconductors MPC5644A, Reference Manual, Page: 1217 / 1735

Decimation Filter
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1217
Section 26.4.2.3, Decimation Filter Module Extended Configuration Register
(DECFILTER_MXCR)
”);
• by software: on software reset, or writing 1 to the DECFILTER_MXCR bit SZRO;
The integrator reset also zeroes the internal counter of accumulated samples and the internal overflow state
(but not SSOVF and SCOVF). Software and hardware reset resets all integrator registers immediately.
Integrator zero command from external signal or by software (SZRO) affects the integrator registers and
flags as follows:
• DECFILTER_CINTVAL resets immediately;
• DECFILTER_CINTCNT does not reset immediately; it is updated only upon a
DECFILTER_CINTVAL read, loaded with the number of integrated samples occurred after the
reset;
• DECFILTER_FINTVAL and DECFILTER_FINTCNT do not reset immediately; being updated
only upon a new output request (see
Section 26.5.15.2, Integrator outputs ”); if a integrator software
zero command (through SZRO bit) and an integrator output request (through SRQ bit) are made at
the same time, the registers DECFILTER_FINTVAL and DECFILTER_FINTCNT are updated
with the last internal values before reset; the same applies to simultaneous integrator zero
command and output request by hardware signal;
• the SSOVF and SCOVF flags do not negate; however, the internal overflow states which assert
SSOVF and SCOVF do reset immediately, so that the next output update (either by hardware
request, software request or DECFILTER_CINTVAL read) before an overflow does not assert
SSOVF/SCOVF.
NOTE
The integrator reset does not depend on the integrator enabling (see
Section 26.5.15.4, Integrator enabling and halting “).
26.5.15.4 Integrator enabling and halting
Two mechanisms, enabling and halting, drive the integrator accumulation, allowing it to be controlled by
a combination of two distinct sources, both software, both hardware, or one hardware and other software.
Values are accumulated when the integrator is enabled and not halted. The integrator halt and enable states
can be controlled in the following ways:
• by hardware, through external signals; the enabling and the selection of the signal request modes
is done through the DECFILTER_MXCR fields SENSEL and SHLTSEL, respectively (see
Section 26.4.2.3, Decimation Filter Module Extended Configuration Register
(DECFILTER_MXCR)
”);
• by software, through the same DECFILTER_MXCR fields SENSEL and SHLTSEL. Note that
these fields are in different bytes, so that two distinct, concurrent software tasks can avoid
coherency problems by changing the fields using byte read-modify-write accesses.
NOTE
Enabling and halting does not affect output requests or integrator reset.