NXP Semiconductors MPC5644A, Reference Manual, Page: 1207 / 1735

Decimation Filter
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1207
Eqn. 26-3
Where all the coefficients are scaled down by S. The block diagram for Equation 26-2 and Equation 26-3
is shown in Figure 26-17 in a fourth-order IIR filter implementation where the coefficients A
j
and B
i
are
called coefficient n , where n = 0-8.
Figure 26-17. Fourth order IIR filter implementation block diagram
The fourth order IIR filter is implemented with a FIR section followed by an IIR section. If the FIR type
filter mode is selected, the IIR section is converted into an FIR section. In this case the order of the FIR
filter is twice the IIR filter order, since all the TAP and coefficient registers are allocated for the FIR
section. The Filter configuration paths are shown in
Figure 26-18 . Multiplexer A controls the bypass filter
path and multiplexer B controls/selects the filter mode of operation, to either IIR mode or FIR mode. The
selection is controlled by the FTYPE[1:0] bits in the Filter Module Configuration register. The order of the
filter can be controlled by setting the appropriate
filter coefficients to zero.
y n
 
S w n
 
A
j
S
-----
y n j –
 
j 1 =
M

+
 
 
 
 
 
=
Z
-1
Z
-1
Z
-1
Z
-1
+
Coefficient 2 Tap1
Coefficient 4
Coefficient 3 Tap2
Tap3
Tap0
Coefficient 0
Coefficient 1
)
+
Coefficient 6 Tap5
Coefficient 8
Coefficient 7 Tap6
Tap7
Tap4
Scale Factor S
Coefficient 5
y
FIR Section IIR Section
Z
-1
Z
-1
Z
-1
Z
-1