NXP Semiconductors MPC5644A, Reference Manual, Page: 1208 / 1735

Decimation Filter
MPC5644A Microcontroller Reference Manual, Rev. 6
1208 Freescale Semiconductor
Figure 26-18. Filter configuration paths (FIR or 1x4 poles IIR)
26.5.6.1 Rounding
The Decimation Filter performs rounding operations in two different locations, as shown in Figure 26-18 :
• to obtain the filter output result with 16 bits
• to obtain the IIR feedback result to be stored in tap4 registers with 24 bits
The rounding mechanism implements the Convergent Rounding methodology (also known as
round-to-nearest even number), which makes the decision on rounding up or down based on the value of
the lower portion of data to be rounded (LS_WORD). The rounding up/down condition is equal to the
traditional rounding except when the LS_WORD has the format {1000...00}. In this particular case, the
rounding procedure is like the example of
Figure 26-19 . If the MS_WORD is odd, the value is rounded
up. Otherwise the value is rounded down.
By-pas
FI
Z
-1
Z
-1
Z
-1
Z
-1
+
Coefficient 2 Tap1
Coefficient 4
Coefficient 3 Tap2
Tap3
Tap0 Coefficient 1
x(n)
+
Coefficient 6 Tap5
Coefficient 8
Coefficient 7 Tap6
Tap7
Tap4 Coefficient 5
y(n)
01 10
B
Z
-1
Z
-1
Z
-1
Z
-1
Round/Sat
FTYPE[1:0]
Round/Sat
IIR
00
A
Scale Factor S
Register Coefficient 0
FIR Section IIR Section