NXP Semiconductors MPC5644A, Reference Manual, Page: 1023 / 1735

Enhanced Queued Analog-to-Digital Converter (EQADC)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1023
Figure 25-5.
EQADC
External Trigger Digital Filter Register (
EQADC
_ETDFR)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0 0 0 0
DFL
W
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Register address: EQA0x00C
Table 25-7.
EQADC
External Trigger Digital Filter Register (
EQADC
_ETDFR) field description
Field Description
28-31
DFL[0:3]
Digital Filter Length
The DFL field specifies the minimum number of system clocks that must be counted by the
digital filter counter to recognize a logic state change. The count specifies the sample period
of the digital filter which is calculated according to the following equation:
Minimum clock counts for which an ETRIG signal needs to be stable to be passed through
the filter are shown in
Table 25-8 . Refer to Section 25.6.4.5, External Trigger Event
Detection , for more information on the digital filter.
Note: The DFL field must only be written when the MODEx of all CFIFOs are configured to
disabled.When the digital filter is bypassed by using the input control, the DFL is not
considered and the trigger input signal is not filtered.
Table 25-8. Minimum Required Time to Valid ETRIG
DFL[0:3] Minimum Clock Count
Minimum Time (ns)
(system clock = 120 MHz)
0b0000 2 16.66
0b0001 3 25.00
0b0010 5 41.66
0b0011 9 75.00
0b0100 17 141.66
0b0101 33 275.00
0b0110 65 541.66
0b0111 129 1075.00
FilterPeriod S

ystemClockPeriod 2
DFL
 
1 S

ystemClockPeriod

+ =