NXP Semiconductors MPC5644A, Reference Manual, Page: 1102 / 1735

Enhanced Queued Analog-to-Digital Converter (EQADC)
MPC5644A Microcontroller Reference Manual, Rev. 6
1102 Freescale Semiconductor
This feature is necessary when the timing of some conversion is very important. In normal priority scheme,
when CFIFO0 is triggered, its conversion command can be put behind 2 pending conversion commands
in the Cbuffer due to the queue structure. Considering that these 2 pending commands are from lower
priority CFIFOs and that the delay between the trigger and the sampling of the command from CFIFO0
can be unacceptable, EQADC can be configured to permit immediate conversion commands from CFIFO0
with abort function.
When CFIFO0 is triggered and abort is enabled, up to 2 commands in Cbuffer0 or Cbuffer1 are stored in
a side register. The abort request signal is generated to ADC0 or ADC1 and the confirmation of ADC
reset/ready is waited to send the command from CFIFO0 to the decoded Cbuffer.
After the transfer of all commands from CFIFO0, the recovery phase restores the up to 2 commands that
were in Cbuffer when the abort occurred. After this recovery phase, it is established the normal process of
prioritization of commands from CFIFOs.
25.6.4.5 External Trigger Event Detection
The digital filters for trigger signals can be individually bypassed by asserting the input control signals
eqadc_intern_trig_sel5-0. When the filter is bypassed, the ETRIG input signal is not filtered and the logic
after the filter receives a copy of this input trigger signal.
The Digital Filter Length field in Section 25.5.2.4, EQADC External Trigger Digital Filter Register
(EQADC_ETDFR) , specifies the minimum number of system clocks that the ETRIG0-5 signals must be
held at a logic level to be recognized as valid. All ETRIG signals are filtered. A counter for each queue
trigger is implemented to detect a transition between logic levels. The counter counts at the system clock
rate. The corresponding counter is cleared and restarted each time the signal transitions between logic
levels. When the corresponding counter matches the value specified by the Digital Filter Length field in
Section 25.5.2.4, EQADC External Trigger Digital Filter Register (EQADC_ETDFR) , the EQADC
considers the ETRIG logic level to be valid and passes that new logic level to the rest of the EQADC.
The filter is only for filtering the ETRIG signal. Logic after the filter checks for transitions between filtered
values, such as for detecting the transition from a filtered logic level zero to a filter logic level one in rising
edge external trigger mode. The EQADC can detect rising edge, falling edge, or level gated external
triggers. The digital filter will always be active independently of the status of the MODE
x field in
Section 25.5.2.7, EQADC CFIFO Control Registers (EQADC_CFCR) , but the edge, level detection logic
is only active when MODEx is set to a value different from disabled, and in case MODEx is set to single
scan mode, when the SSS bit is asserted. Note that the time necessary for a external trigger event to result
into a CFIFO status change is not solely determined by the DFL field in the
Section 25.5.2.4, EQADC
External Trigger Digital Filter Register (EQADC_ETDFR) . After being synchronized to the system clock
and filtered, a trigger event is checked against the CFIFO trigger mode. Only then, after a valid trigger
event is detected, the EQADC accordingly changes the CFIFO status. Refer to
Figure 25-66 for an
example.