NXP Semiconductors MPC5605BK, Reference Manual

Page: 660 / 964

Chapter 27 Timers
MPC5606BK Microcontroller Reference Manual, Rev. 2
658 Freescale Semiconductor
Figure 27-7. Channel configuration
27.4.1.4.1 Channel mode selection
Channel modes are selected using the mode selection bits MODE[0:6] in the eMIOS UC Control Register
(EMIOSC[n]).
Table 27-21 provides the specific mode selection settings for the eMIOS implementation
on this device.
27.4.2 External signal description
For information on eMIOS external signals on this device, please refer to Chapter 4, Signal description .
27.4.3 Memory map and register description
27.4.3.1 Memory maps
The overall address map organization is shown in Table 27-9 .
27.4.3.1.1 Unified Channel memory map
Table 27-9. eMIOS memory map
Base addresses:
0xC3FA_0000 (eMIOS_0)
0xC3FA_4000 (eMIOS_1)
Address offset Description Location
0x000–0x003 eMIOS Module Configuration Register (EMIOSMCR) on page 659
0x004–0x007 eMIOS Global FLAG (EMIOSGFLAG) Register on page 660
0x008–0x00B eMIOS Output Update Disable (EMIOSOUDIS) Register on page 661
0x00C–0x00F eMIOS Disable Channel (EMIOSUCDIS) Register on page 662
0x010–0x01F Reserved —
0x020–0x11F Channel [0]
to
Channel [7]
—
0x120–0x21F Channel [8]
to
Channel [15]
—
0x220–0x31F Channel [16]
to
Channel [23]
—
0x320–0x41F Channel [24]
to
Channel [31]
0x420–0xFFF Reserved