NXP Semiconductors MPC5605BK, Reference Manual

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Chapter 27 Timers
MPC5606BK Microcontroller Reference Manual, Rev. 2
660 Freescale Semiconductor
27.4.3.2.2 eMIOS Global FLAG (EMIOSGFLAG) Register
The EMIOSGFLAG is a read-only register that groups the flag bits (F[31:0]) from all channels. This
organization improves interrupt handling on simpler devices. Each bit relates to one channel.
For Unified Channels these bits are mirrors of the FLAG bits in the EMIOSS[n] register.
FRZ Freeze
Enables the eMIOS to freeze the registers of the Unified Channels when Debug Mode is requested
at MCU level. Each Unified Channel should have FREN bit set in order to enter freeze state. While
in Freeze state, the eMIOS continues to operate to allow the MCU access to the Unified Channels
registers. The Unified Channel will remain frozen until the FRZ bit is written to 0 or the MCU exits
Debug mode or the Unified Channel FREN bit is cleared.
1 = Stops Unified Channels operation when in Debug mode and the FREN bit is set in the
EMIOSC[n] register
0 = Exit freeze state
GTBE Global Time Base Enable
The GTBE bit is used to export a Global Time Base Enable from the module and provide a method
to start time bases of several blocks simultaneously.
1 = Global Time Base Enable Out signal asserted
0 = Global Time Base Enable Out signal negated
Note: The Global Time Base Enable input pin controls the internal counters. When asserted,
Internal counters are enabled. When negated, Internal counters disabled.
GPREN Global Prescaler Enable
The GPREN bit enables the prescaler counter.
1 = Prescaler enabled
0 = Prescaler disabled (no clock) and prescaler counter is cleared
GPRE Global Prescaler
The GPRE bits select the clock divider value for the global prescaler, as shown in
Table 27-12 .
Table 27-12. Global prescaler clock divider
GPRE Divide ratio
00000000 1
00000001 2
00000010 3
00000011 4
.
.
.
. .
.
.
.
11111110 255
11111111 256
Table 27-11. EMIOSMCR field descriptions (continued)
Field Description