NXP Semiconductors MPC5605BK, Reference Manual

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Chapter 26 Deserial Serial Peripheral Interface (DSPI)
MPC5606BK Microcontroller Reference Manual, Rev. 2
598 Freescale Semiconductor
26.5.2 DSPI Module Configuration Register (DSPI x _MCR)
The DSPI x _MCR contains bits that configure attributes of the DSPI operation. The values of the HALT
and MDIS bits can be changed at any time, but their effect begins on the next frame boundary. The HALT
and MDIS bits in the DSPI
x _MCR are the only bit values software can change while the DSPI is running.
Table 26-2. DSPI memory map
Base addresses:
0xFFF9_0000 (DSPI_0)
0xFFF9_4000 (DSPI_1)
0xFFF9_8000 (DSPI_2)
0xFFF9_C000 (DSPI_3)
0xFFFA_0000 (DSPI_4)
0xFFFA_4000 (DSPI_5)
Address offset Register Location
0x00 DSPI Module Configuration Register (DSPI x _MCR) on page 598
0x04 Reserved
0x08 DSPI Transfer Count Register (DSPI x _TCR) on page 601
0x0C DSPI Clock and Transfer Attributes Register 0 (DSPI x _CTAR0) on page 602
0x10 DSPI Clock and Transfer Attributes Register 1 (DSPI x _CTAR1) on page 602
0x14 DSPI Clock and Transfer Attributes Register 2 (DSPI x _CTAR2) on page 602
0x18 DSPI Clock and Transfer Attributes Register 3 (DSPI x _CTAR3) on page 602
0x1C DSPI Clock and Transfer Attributes Register 4 (DSPI x _CTAR4) on page 602
0x20 DSPI Clock and Transfer Attributes Register 5 (DSPI x _CTAR5) on page 602
0x24–0x28 Reserved
0x2C DSPI Status Register (DSPI x _SR) on page 610
0x30 DSPI DMA / Interrupt Request Select and Enable Register
(DSPIx_RSER) on page 612
0x34 DSPI Push TX FIFO Register (DSPI x _PUSHR) on page 614
0x38 DSPI Pop RX FIFO Register (DSPI x _POPR) on page 616
0x3C DSPI Transmit FIFO Register 0 (DSPI x _TXFR0) on page 617
0x40 DSPI Transmit FIFO Register 1 (DSPI x _TXFR1) on page 617
0x44 DSPI Transmit FIFO Register 2 (DSPI x _TXFR2) on page 617
0x48 DSPI Transmit FIFO Register 3 (DSPI x _TXFR3) on page 617
0x4C–0x78 Reserved
0x7C DSPI Receive FIFO Register 0 (DSPI x _RXFR0) on page 617
0x80 DSPI Receive FIFO Register 1 (DSPI x _RXFR1) on page 617
0x84 DSPI Receive FIFO Register 2 (DSPI x _RXFR2) on page 617
0x88 DSPI Receive FIFO Register 3 (DSPI x _RXFR3) on page 617