NXP Semiconductors MKW01Z128, Reference Manual

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• External clock monitor with reset and interrupt request capability to check for
external clock failure when running in FBE, PEE, BLPE, or FEE modes
• Lock detector with interrupt request capability for use with the PLL
• Internal Reference Clocks Auto Trim Machine (ATM) capability using an external
clock as a reference
• Reference dividers for both the FLL and the PLL are provided
• Reference dividers for the Fast Internal Reference Clock are provided
• MCG PLL Clock (MCGPLLCLK) is provided as a clock source for other on-chip
peripherals
• MCG FLL Clock (MCGFLLCLK) is provided as a clock source for other on-chip
peripherals
• MCG Fixed Frequency Clock (MCGFFCLK) is provided as a clock source for other
on-chip peripherals
• MCG Internal Reference Clock (MCGIRCLK) is provided as a clock source for other
on-chip peripherals
This figure presents the block diagram of the MCG module.
Figure 20-1. Multipurpose Clock Generator (MCG) block diagram
NOTE
Refer to the chip configuration chapter to identify the oscillator
used in this MCU.
20.1.2 Modes of Operation
The MCG has the following modes of operation: FEI, FEE, FBI, FBE, PBE, PEE, BLPI,
BLPE, and Stop. For details, see
MCG modes of operation .
20.2 External Signal Description
There are no MCG signals that connect off chip.
Chapter 20 Multipurpose Clock Generator (MCG)
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
Freescale Semiconductor, Inc. 337