NXP Semiconductors MKW01Z128, Reference Manual

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MKW01Z128 Transceiver - MCU SPI Interface
MKW01xxRM Reference Manual, Rev. 3, 04/2016
Freescale Semiconductor, Inc. 8-3
8.3.1 SPI Signal Definitions
The SPI signals of SS, SCK, MOSI, and MISO are defined in the following paragraphs.
8.3.1.1 Slave Select (SS or NSS)
A transaction on the SPI port is framed by the active low Slave Select (SS) input signal which is driven by
the MCU as master.
8.3.1.2 SPI Clock (SCK or SPSCK)
The host drives the SPI Clock (SCK) input to the transceiver. Data is clocked into the master or slave on
the leading (rising) edge of the return-to-zero SPSCK and data changes state on the trailing (falling) edge
of SPSCK.
NOTE
• The SPI Bus protocol as defined by the Motorola/Freescale standard
supports other clock/data timing, however, the described mode is the
only one used.
• For the MKW0xxx microcontroller, the SPI clock format is the clock
phase control bit CPHA = 0 and the clock polarity control bit CPOL = 0.
8.3.1.3 Master Out / Slave In (MOSI)
The Master Out/Slave In (MOSI) signal presents incoming data from the host to the transceiver (slave
input).
8.3.1.4 Master In / Slave Out (MISO)
The Master In/Slave Out (MISO) signal presents incoming data from the transceiver to the MCU (master
input).
8.3.2 MKW0xxx SPI Transaction Protocol
Although standard SPI protocol is based on 8-bit transfers, the transceiver imposes a higher level
transaction protocol that is based on multiple 8-bit transfers per transaction. There are three SPI transaction
modes defined to access the transceiver registers:
• SINGLE access - an address byte is followed by a data byte
— For a write access, the data byte (MOSI) is written to the addressed transceiver register
— For a read access, the data byte (MISO) is read from the addressed transceiver register
— The NSS pin goes low at the beginning of the frame and goes high after the data byte
• BURST access - an address byte is followed by several data bytes.
— The address byte provides the starting register address for the data burst
— The address is automatically incremented internally between each data byte.
— This mode supports both read and write accesses.