NXP Semiconductors MIMXRT1060, Hardware User'S Manual, Page: 12 / 19

The boot from QSPI flash only supports RT1060.
NOTE
2.8 Ethernet connector
There are two Ethernet Mac controllers in the MIMXRT1060/1064 processor. The Ethernet subsystem of the MIMXRT1060/1064
EVK board is provided by the KSZ8081RNB 10/100 M Ethernet Transceiver (U16) and an RJ45 (J19) with integrated magnetic.
2.9 USB PHY connector
MIMXRT1060/1064 contains two integrated USB 2.0 PHYs capable of connecting USB host/device systems at:
• USB low-speed (LS) rate of 1.5 Mbits/s
• USB full-speed (FS) rate of 12 Mbits/s
• USB 2.0 high-speed (HS) rate of 480 Mbits/s
2.10 Audio input/output connector
The audio codec used on the MIMXRT1060/1064 EVK board is Wolfson’s low power, high-quality stereo codec, WM8960.
The MIMXRT1060/1064 EVK board includes:
• one headphone interface (J12)
• one onboard MIC (P1)
• two speaker interfaces (J16, J17)
• S/PDIF interface (J14 and J18, DNP).
J12 is a 3.5 mm audio-stereo headphone jack, which supports jack detect.
NOTE
2.11 OpenSDA circuit (DAP-Link)
The OpenSDA circuit (CMSIS–DAP) is an open-standard serial and debug adapter. It bridges serial and debug communications
between a USB host and an embedded target processor.
CMSIS-DAP features a mass storage device (MSD) bootloader, which provides a quick and easy mechanism for loading different
CMSIS-DAP applications such as flash programmers, run-control debug interfaces, serial-to-USB converters, and more.
Two or more CMSIS-DAP applications can run simultaneously. For example, run-control debug application and serial-to-USB
converter run in parallel to provide a virtual COM communication interface while allowing code debugging via CMSIS-DAP with
single USB connection.
For the MIMXRT1060/1064 EVK board, J41 is the connector between the USB host and the RT1060/1064. To update the Open
SDA firmaware, press the SW8 and Power on the board. There is a disk named "MAINTENANCE". Drag/drop the new firmware
to the "MAINTENANCE" and re-power the board. The firmware is updated.
2.12 JTAG connector
J21 is a standard 20-pin/2.54 mm box header connector JTAG. The pin definitions are shown in Figure 6 . It supports SWD by
default.
NXP Semiconductors
Specifications
MIMXRT1060/1064 Evaluation Kit Board Hardware User's Guide, Rev. 0, 06/2020
User's Guide 12 / 19