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Physical Layer Interface Controller (PLIC)
MCF5272 ColdFire
®
Integrated Microprocessor User’s Manual, Rev. 3
13-42
Freescale Semiconductor
Two of Freescale’s MC145574 S/T transceivers are shown connected to ports 0 and 1. The frame sync
control signal FSC0 is connected to S/T transceiver one, while FSC1 is connected to transceiver two.
shows an example of the IDL bus timing relationship of the S/T transceivers when in
standard IDL2 8-bit mode with a common frame sync.
Figure 13-42. Standard IDL2 8-Bit Mode
B1
B2
D
MC145574 #1
DCL
FSC0
FSC1
Din0/
Din1/
Dout1
Dout0
B1
B2
D
MC145574 #2