NXP Semiconductors MC9S12XS128, Reference Manual

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Electrical Characteristics
S12XS Family Reference Manual, Rev. 1.13
692 Freescale Semiconductor
For N < 1000, the following equation is a good fit for the maximum jitter:
Figure A-5. Maximum bus clock jitter approximation
NOTE
On timers and serial modules a prescaler will eliminate the effect of the jitter
to a large extent.
Table A-24. IPLL Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C Rating Symbol Min Typ Max Unit
1 P Self Clock Mode frequency
1
1
Bus frequency is equivalent to f
SCM
/2
f
SCM
1 — 4 MHz
2 T VCO locking range
f
VCO
32 — 120 MHz
3 T Reference Clock
f
REF
1 — 40 MHz
4 D Lock Detection
|∆
Lock
|
0 — 1.5
%
2
2
% deviation from target frequency
5 D Un-Lock Detection
|∆
unl
|
0.5 — 2.5
%
2
7 C Time to lock
t
lock
— 214
150 +
256/f
REF
µ
s
8 C Jitter fit parameter 1
3
3
f
OSC
=4MHz, f
BUS
=40MHz equivalent f
PLL
=80MHz: REFDIV=$00, REFRQ=01, SYNDIV=$09, VCOFRQ=01, POSTDIV=$00
j
1
— — 1.2 %
9 C Jitter fit parameter 2
3 j
2
— — 0 %
10 C Bus Frequency for FM1=1, FM0=1 (frequency
modulation in PLLCTL register of s12xe_crg)
f
bus
— — 38 MHz
11 C Bus Frequency for FM1=1, FM0=0 (frequency
modulation in PLLCTL register of s12xe_crg)
f
bus
— — 39 MHz
12 C Bus Frequency for FM1=0, FM0=1 (frequency
modulation in PLLCTL register of s12xe_crg)
f
bus
— — 39 MHz
J N
( )
j
1
N
--------
j
2
+ =
1 5 10 20 N
J(N)