NXP Semiconductors MC9S12VRP64, Owner Reference Manual

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Serial Communication Interface (S12SCIV6)
MC9S12VRP Family Reference Manual Rev. 1.3
NXP Semiconductors 333
10.4.6.5.2 Fast Data Tolerance
Figure 10-29 shows how much a fast received frame can be misaligned. The fast stop bit ends at RT10
instead of RT16 but is still sampled at RT8, RT9, and RT10.
Figure 10-29. Fast Data
For an 8-bit data character, it takes the receiver 9 bit times x 16 RTr 9 RTr cycles = 153 RTr cycles
to finish data sampling of the stop bit.
With the misaligned character shown in Figure 10-29 , the receiver counts 153 RTr cycles at the point when
the count of the transmitting device is 10 bit times x 16 RTt cycles = 160 RTt cycles.
The maximum percent difference between the receiver count and the transmitter count of a fast 8-bit
character with no errors is:
((160 – 153) / 160) x 100 = 4.375%
For a 9-bit data character, it takes the receiver 10 bit times x 16 RTr 9 RTr cycles = 169 RTr cycles
to finish data sampling of the stop bit.
With the misaligned character shown in Figure 10-29 , the receiver counts 169 RTr cycles at the point when
the count of the transmitting device is 11 bit times x 16 RTt cycles = 176 RTt cycles.
The maximum percent difference between the receiver count and the transmitter count of a fast 9-bit
character with no errors is:
((176 – 169) /176) x 100 = 3.98%
NOTE
Due to asynchronous sample and internal logic, there is maximal 2 bus
cycles between startbit edge and 1st RT clock, and cause to additional
tolerance loss at worst case. The loss should be 2/SBR/10*100%, it is
small.For example, for highspeed baud=230400 with 25MHz bus, SBR
should be 109, and the tolerance loss is 2/109/10*100=0.18%, and fast data
tolerance is 4.375%-0.18%=4.195%.
10.4.6.6 Receiver Wakeup
To enable the SCI to ignore transmissions intended only for other receivers in multiple-receiver systems,
the receiver can be put into a standby state. Setting the receiver wakeup bit, RWU, in SCI control register 2
(SCICR2) puts the receiver into standby state during which receiver interrupts are disabled.The SCI will
still load the receive data into the SCIDRH/L registers, but it will not set the RDRF flag.
Idle or Next Frame Stop
RT
1
RT
2
RT
3
RT
4
RT
5
RT
6
RT
7
RT
8
RT
9
RT
10
RT
11
RT
12
RT
13
RT
14
RT
15
RT
16
Data
Samples
Receiver
RT Clock