NXP Semiconductors MC9S08QL4, Reference Manual

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Timer/Pulse-Width Modulator (S08TPMV3)
MC9S08QL8 MCU Series Reference Manual, Rev. 1
212 NXP Semiconductors
15.3.2 TPM-Counter Registers (TPMxCNTH:TPMxCNTL)
The two read-only TPM counter registers contain the high and low bytes of the value in the TPM counter.
Reading either byte (TPMxCNTH or TPMxCNTL) latches the contents of both bytes into a buffer where
they remain latched until the other half is read. This allows coherent 16-bit reads in big-endian or
little-endian order that makes this more friendly to various compiler implementations. The coherency
mechanism is automatically restarted by an MCU reset or any write to the timer status/control register
(TPMxSC).
Reset clears the TPM counter registers. Writing any value to TPMxCNTH or TPMxCNTL also clears the
TPM counter (TPMxCNTH:TPMxCNTL) and resets the coherency mechanism, regardless of the data
involved in the write.
01 Bus clock
10 Fixed frequency clock
11 External clock
Table 15-7. Prescale Factor Selection
PS[2:0] TPM Clock Divided-by
000 1
001 2
010 4
011 8
100 16
101 32
110 64
111 128
7 6 5 4 3 2 1 0
R TPMxCNT[15:8]
W Any write to TPMxCNTH clears the 16-bit counter
Reset 0 0 0 0 0 0 0 0
Figure 15-7. TPM Counter Register High (TPMxCNTH)
Table 15-6. TPM Clock Selection
CLKSB:CLKSA TPM Clock to Prescaler Input