UM11029
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User manual
Rev. 1.0 — 16 June 2017
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NXP Semiconductors
UM11029
Chapter 21: LPC84x SCTimer/PWM
21.6.23 SCTimer/PWM capture control registers 0 to 7 (REGMODEn bit = 1)
If UNIFY = 1 in the CONFIG register, only the _L bits are used.
If UNIFY = 0 in the CONFIG register, this register can be written to as two registers
CAPCTRLn_L and CAPCTRLn_H. Both the L and H registers can be read or written
individually or in a single 32-bit read or write operation.
The capture registers can be loaded with the current counter value when any of the
specified events occur.
Each Capture Control register (L, H, or unified 32-bit) controls which events cause loading
of the corresponding Capture register from the counter.
21.6.24 SCTimer/PWM event enable registers 0 to 7
Each event can be enabled in some contexts (or states) and disabled in others. Each
event defined in the EV_CTRL register has one associated event enable register that can
enable or disable the event for each available state.
An event n is completely disabled when its EVn_STATE register contains all zeros, since it
is masked regardless of the current state.
In simple applications that do not use states, writing 0x01 (or any other value with a 1 in bit
0) will enable the event. Since the state doesn’t change (that is, the state variable always
remains at its reset value of 0), setting bit 0 permanently enables this event. Conversely,
clearing bit 0 will disable the event.
Table 407. SCTimer/PWM match reload registers 0 to 7 (MATCHREL[0:7], offset 0x200
(MATCHREL0) to 0x21C (MATCHREL7)) bit description (REGMODEn bit = 0)
Bit
Symbol
Description
Reset
value
15:0
RELOADn_L When UNIFY = 0, specifies the 16-bit value to be loaded into the
MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits
of the 32-bit value to be loaded into the MATCHn register.
0
31:16 RELOADn_H When UNIFY = 0, specifies the 16-bit to be loaded into the
MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits
of the 32-bit value to be loaded into the MATCHn register.
0
Table 408. SCTimer/PWM capture control registers 0 to 7 (CAPCTRL[0:7], offset 0x200
(CAPCTRL0) to 0x21C (CAPCTRL7)) bit description (REGMODEn bit = 1)
Bit
Symbol
Description
Reset
value
7:0
CAPCONn_L
If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the
CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1
= bit 1,..., event 7 = bit 7).
0
15:8
-
Reserved.
-
23:16
CAPCONn_H
If bit m is one, event m causes the CAPn_H (UNIFY = 0)
register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event
7 = bit 23).
0
31:24
-
Reserved.
-
