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UM11029

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User manual

Rev. 1.0 — 16 June 2017

25 of 515

NXP Semiconductors

UM11029

Chapter 5: LPC84x ISP and IAP

If FAIM content is invalid, the default ISP selection is USART/I2C/SPI or auto detection
mode. In auto detection mode, the LPC84x enables all three interfaces on the fixed GPIO
port and pins, and selects the first one that has either a successful auto baud detection on
USART or a valid probe message response on I2C or SPI.

If FAIM content is valid, USART, I2C, or SPI ISP mode is configured in the FAIM.
Additional SWM configuration for the interface and pins through FAIM is required. For
example, if FAIM ISP selection is 0x02, the GPIO port and pin information for SPI0, such
as SSEL, SCK, MOSI, and MISO is provided by the FAIM. The boot ROM reads the GPIO
port and pin information from the FAIM and writes to the SWM and IOCON registers
accordingly as part of the SPI initialization.

5.3.7 ISP interrupt and SRAM use

5.3.7.1 Interrupts during IAP

The on-chip flash memory is not accessible during erase/write operations. When the user
application code starts executing, the interrupt vectors from the user flash area are active.
Before making any IAP call, either disable the interrupts or ensure that the user interrupt
vectors are active in RAM and that the interrupt handlers reside in RAM. The IAP code
does not use or disable interrupts.

5.3.7.2 RAM used by ISP command handlers

The stack of UART ISP commands is located at address 0x1000 0600. The maximum
stack usage is 1280 bytes (0x500) and grows downwards.

The DMA is used by the SPI ISP mode. The DMA descriptor table location is located at
address 0x1000 0600. The DMA table size is 512 bytes (0x200) and grows upwards.
Therefore, depending on the ISP mode entered, the maximum RAM used by ISP mode is
2 K starting from the address 0x1000 0000.

Memory for the USART and I2C/SPI ISP commands is allocated dynamically.

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Summary of Contents for LPC84x

Page 1: ...UM11029 LPC84x User manual Rev 1 0 16 June 2017 User manual Document information Info Content Keywords LPC84x LPC84x UM LPC84x user manual Abstract LPC84x User manual ...

Page 2: ...erved User manual Rev 1 0 16 June 2017 2 of 515 Contact information For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com NXP Semiconductors UM11029 LPC84x User manual Revision history Rev Date Description v 1 20170616 Initial revision LPC84x User manual ...

Page 3: ...stem ARM Cortex M0 processor revision r0p1 running at frequencies of up to 30 MHz with single cycle multiplier and fast single cycle I O port ARM Cortex M0 built in Nested Vectored Interrupt Controller NVIC System tick timer AHB multilayer matrix Serial Wire Debug SWD with four break points and two watch points JTAG boundary scan BSDL supported Micro Trace Buffer MTB Memory Up to 64 KB on chip fla...

Page 4: ...his document is subject to legal disclaimers NXP Semiconductors N V 2017 All rights reserved User manual Rev 1 0 16 June 2017 4 of 515 NXP Semiconductors UM11029 Chapter 1 LPC84x Introductory information On chip ROM APIs for integer divide ...

Page 5: ...d internally to or from selected peripherals Internally the SCTimer PWM supports 8 match captures 8 events and 8 states One 32 bit general purpose counter timer with four match outputs and three capture inputs Supports PWM mode external count and DMA Four channel Multi Rate Timer MRT for repetitive interrupt generation at up to four programmable fixed rates Self Wake up Timer WKT clocked from eith...

Page 6: ... 25 MHz Low power oscillator can be used as a clock source to the watchdog timer Programmable watchdog oscillator with a frequency range of 9 4 kHz to 2 3 MHz PLL allows CPU operation up to the maximum CPU rate without the need for a high frequency crystal May be run from the system oscillator the external clock input or the internal FRO Clock output function with divider that can reflect all inte...

Page 7: ...age 48 leads body 7 7 1 4 mm SOT313 2 LPC845M301JHI48 HVQFN48 HVQFN plastic thermal enhanced very thin quad flat package no leads 48 terminals body 7 7 0 85 mm SOT619 1 LPC845M301JHI33 HVQFN33 HVQFN plastic thermal enhanced very thin quad flat package no leads 33 terminals body 5 5 0 85 mm SOT617 11 LPC844M201JBD64 LQFP64 Plastic low profile quad flat package 64 leads body 10 10 1 4 mm SOT314 2 LP...

Page 8: ...lator DEBUG INTERFACE IOP bus GPIOs GPIOs AND GPOINT Flash interface Flash 64 kB General Purpose DMA controller MTB slave interface DMA registers CRC Multilayer AHB Matrix AHB to APB bridge FAIM 256 bit T0 Match Capture I2C2 3 COMP Inputs ADC Inputs and Triggers DAC1 outputs DAC0 outputs PIOs UART0 1 2 3 4 SPI0 1 I2C0 1 APB slave group Watchdog Osc Windowed WDT Note SCT Timer PWM ARM Cortex M0 Sys...

Page 9: ...re 2 shows the overall map of the entire address space from the user program viewpoint following reset The APB peripheral area is 512 KB in size and is divided to allow for up to 32 peripherals Each peripheral is allocated 16 KB of space simplifying the address decoding The registers incorporated into the ARM Cortex M0 core such as NVIC SysTick and sleep mode control are located on the private per...

Page 10: ... FFFF 0xE010 0000 0xE000 0000 0xA008 0000 0xA004 0000 0xA000 0000 0x5001 4000 0x5000 0000 0x4008 0000 0x4000 0000 0x1000 4000 0x1000 2000 0x1000 0000 0x0F00 4000 0x0F00 0000 0x0001 0000 0x0000 0000 0x0000 00C0 0x0000 0000 reserved UART4 UART3 UART2 APB perpherals UART1 UART0 reserved SPI1 SPI0 I2C1 I2C0 reserved Syscon IOCON Flash controller reserved CTIMER 0 I2C3 I2C2 Input Multiplexing reserved ...

Page 11: ...r to select the operating frequency accordingly If FAIM is not programmed or contains an invalid value the ROM begins at 12 MHz 3 4 Pin description When the ISP entry pin PIO0_12 is pulled LOW on reset the part enters ISP mode and the ISP command handler starts up UM11029 Chapter 3 LPC84x Boot Process Rev 1 0 16 June 2017 User manual Table 3 Pin location in ISP mode ISP mode Default FAIM configura...

Page 12: ... SPI master connections During the boot process a LOW level after reset on the ISP pin is considered as an external hardware request to start the ISP command handler via USART I2C or SPI interface Otherwise the bootloader checks if there is valid user code in flash If the valid user code is not found the bootloader checks the FAIM configuration and enters one of the ISP modes Auto detect is select...

Page 13: ...structure 0x0 0x4 0x8 0x10 0xC Device API 3 Power profiles API function table IAP calls Clock setting and enter low power mode API aaa 026624 Ptr to IAP 0x0F001FF1 Ptr to ROM Driver table 0x0F001FF8 ROM Driver Table Reserved Reserved Reserved Ptr to Device API Table n Device API n Ptr to Function 0 Ptr to Function 1 Ptr to Function 2 Ptr to Function n Device API 4 Integer Divide routines function ...

Page 14: ...BASE 0x0F001FF8 3 6 Functional description 3 6 1 Memory map after any reset The boot ROM block is 16 KB in size The boot block is located in the memory region starting from address 0x0F00 0000 The bootloader is designed to run from this memory area but both the ISP and IAP software use parts of the on chip RAM The RAM usage is described in Section 4 3 7 ISP interrupt and SRAM use The interrupt vec...

Page 15: ...FAIM content invalid fixed USART I2C SPI port pins FAIM ISP select 0 USART port pin setting FAIM ISP select 0 USART port pin setting FAIM ISP select 2 SPI port pin setting UART ISP USART ISP command handler I2C SPI ISP command handler I2C ISP User code SPI ISP Device configure Initialize CRP 1 2 3 enabled WDT reset No_ISP or CRP3 enabled no no no 0 1 2 invalid 2 1 0 no no User code valid User code...

Page 16: ...ng the ROM IAP calls FAIMWrite and FAIMRead see Chapter 5 LPC84x ISP and IAP for details After a FAIMMWrite a FAIMRead is required to update the output of the FAIM Once a read has been performed the FAIM contents are visible in the AHB Peripheral address space starting at 0x5001_0000 For the pull up pull down and HI Z IOCON pin configuration settings a reset is needed to transfer the newly program...

Page 17: ...9 27 FAIM content valid bits 11 00 FAIM content invalid 01 FAIM content invalid 10 FAIM content invalid 11 FAIM content valid 31 30 ISP interface select 0 00 USART0 01 I2C0 10 SPI0 11 Reserved Table 6 FAIM word 1 bit description Bit Description Default value 4 0 ISP Rx pin select USART0 Rx SPI MOSI 0x18 0x0 0x1 0x1F PIOn_0 PIOn_1 PIOn_31 7 5 ISP Rx port select USART0 Rx SPI MOSI 0 0x0 Port 0 0x1 P...

Page 18: ... word 3 bit description Bit Description Default value 31 0 Reserved 0 Table 9 FAIM word 4 bit description Bit Description Default value 19 0 Reserved 0 21 20 PIO1_21 0x2 0x0 Hi Z 0x1 Pull down 0x2 Pull up 0x3 Repeater 23 22 PIO1_20 See description of bits of bits 21 20 0x2 25 24 PIO1_19 See description of bits 21 20 0x2 27 26 PIO1_18 See description of bits 21 20 0x2 29 28 PIO1_17 See description ...

Page 19: ... PIO1_1 See description of bits 1 0 0x2 31 30 PIO1_0 See description of bits 1 0 0x2 Table 11 FAIM word 6 bit description Bit Description Default value 1 0 PIO0_31 0 0x0 Hi Z 0x2 0x1 Pull down 0x2 Pull up 0x3 Repeater 3 2 PIO0_30 See description of bits 1 0 0x2 5 4 PIO0_29 See description of bits 1 0 0x2 7 6 PIO0_28 See description of bits 1 0 0x2 9 8 PIO0_27 See description of bits 1 0 0x2 11 10 ...

Page 20: ...ee description of bits 1 0 0x2 7 6 PIO0_12 See description of bits 1 0 0x2 9 8 PIO0_11 See description of bits 1 0 0x2 11 10 PIO0_10 See description of bits 1 0 0x2 13 12 PIO0_9 See description of bits 1 0 0x2 15 14 PIO0_8 See description of bits 1 0 0x2 17 16 PIO0_7 See description of bits 1 0 0x2 19 18 PIO0_6 See description of bits 1 0 0x2 21 20 PIO0_5 See description of bits 1 0 0x2 23 22 PIO0...

Page 21: ...ing ISP is programming or reprogramming the on chip flash memory using the boot loader software and USART I2C or SPI serial port This can be done when the part resides in the end user board In Application Programming In Application IAP programming is performing erase and write operation on the on chip flash memory as directed by the end user application code Flexible ISP mode and port pin selectio...

Page 22: ...equest into the user s Flash is made write of user specified content is accompanied by a matching ECC value calculated and stored in the ECC memory When a sector of Flash memory is erased the corresponding ECC bytes are also erased Once an ECC byte is written it can not be updated unless it is erased first Therefore for the implemented ECC mechanism to perform properly data must be written into th...

Page 23: ... yes yes 9 1 144 159 0x0000 2400 0x0000 27FF yes yes 10 1 160 175 0x0000 2800 0x0000 2BFF yes yes 11 1 176 191 0x0000 2C00 0x0000 2FFF yes yes 12 1 192 207 0x0000 3000 0x0000 33FF yes yes 13 1 208 223 0x0000 3400 0x0000 37FF yes yes 14 1 224 239 0x0000 3800 0x0000 3BFF yes yes 15 1 240 255 0x0000 3C00 0x0000 3FFF yes yes 16 1 256 271 0x0000 4000 0x0000 43FF yes 17 1 272 287 0x0000 4400 0x0000 47FF...

Page 24: ...or entering ISP mode ISP sampling pin is available for other applications CRP1 0x1234 5678 Access to chip via the SWD pins is disabled This mode allows partial flash update using the following USART ISP commands and restrictions Write to RAM command cannot access RAM below 0x1000 0600 Access to addresses below 0x1000 0600 is disabled Copy RAM to flash command cannot write to Sector 0 Erase command...

Page 25: ...tion from the FAIM and writes to the SWM and IOCON registers accordingly as part of the SPI initialization 5 3 7 ISP interrupt and SRAM use 5 3 7 1 Interrupts during IAP The on chip flash memory is not accessible during erase write operations When the user application code starts executing the interrupt vectors from the user flash area are active Before making any IAP call either disable the inter...

Page 26: ...F The auto baud routine looks at the received characters to verify synchronization If synchronization is verified then OK CR LF string is sent to the host The host should respond by sending the crystal frequency in kHz at which the part is running The response is required for backward compatibility of the boot loader code and is ignored OK CR LF string is sent to the host after receiving the cryst...

Page 27: ...Baud Rate B Baud Rate stop bit 5 5 2 Echo A setting 5 5 3 Write to RAM W start address number of bytes 5 5 4 Read Memory R address number of bytes 5 5 5 Prepare sectors for write operation P start sector number end sector number 5 5 6 Copy RAM to flash C Flash address RAM address number of bytes 5 5 7 Go G address Mode 5 5 8 Erase sector s E start sector number end sector number 5 5 9 Erase page s...

Page 28: ...only no n a Read Write FAIM page yes yes n a Table 16 ISP commands allowed for different CRP levels ISP command CRP1 CRP2 CRP3 no entry in ISP mode allowed Table 17 USART ISP Unlock command Command U Input Unlock code 2313010 Return Code CMD_SUCCESS INVALID_CODE PARAM_ERROR Description This command is used to unlock Flash Write Erase and Go commands Example U 23130 CR LF unlocks the Flash Write Er...

Page 29: ...mber of Bytes Number of bytes to be written Count should be a multiple of 4 Return Code CMD_SUCCESS ADDR_ERROR Address not on word boundary ADDR_NOT_MAPPED COUNT_ERROR Byte count is not multiple of 4 PARAM_ERROR CODE_READ_PROTECTION_ENABLED Description This command is used to download data to RAM This command is blocked when code read protection levels 2 or 3 are enabled Writing to addresses below...

Page 30: ...nce a mechanism intrinsic to flash memories an erase should be performed after 16 consecutive writes inside the same page Note that the erase operation then erases the entire sector Remark Once a page has been written to 16 times it is still possible to write to other pages within the same sector without performing a sector erase assuming that those pages have been erased previously Table 22 USART...

Page 31: ...and is used to program the flash memory The Prepare Sector s for Write Operation command should precede this command The affected sectors are automatically protected again once the copy command is successfully executed This command is blocked when code read protection is enabled Also see Section 5 3 3 for the number of bytes that can be written Example C 0 268437504 512 CR LF copies 512 bytes from...

Page 32: ... enabled Example E 2 3 CR LF erases the flash sectors 2 and 3 Table 26 USART ISP Erase page command Command X Input Start Page Number End Page Number Should be greater than or equal to start page number Return Code CMD_SUCCESS BUSY INVALID_PAGE SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION CMD_LOCKED PARAM_ERROR CODE_READ_PROTECTION_ENABLED Description This command is used to erase one or more page s of...

Page 33: ... version number command Command K Input None Return Code CMD_SUCCESS followed by 2 bytes of boot code version number in ASCII format It is to be interpreted as byte1 Major byte0 Minor Description This command is used to read the boot code version number Table 31 USART ISP Compare command Command M Input Address1 DST Starting flash or RAM address of data bytes to be compared This address should be ...

Page 34: ...nput None Return Code CMD_SUCCESS followed by four 32 bit words of a unique serial number in ASCII format The word sent at the lowest address is sent first Description This command is used to read the unique ID Table 33 USART ISP Read CRC checksum command Command S Input Address The data are read from this address for CRC checksum calculation This address must be on a word boundary Number of Bytes...

Page 35: ...is enabled End address End of flash address Default 0xFFFF Must be 0xFFFF when CRP1 is enabled Number of wait states Number of wait states Default 2 Mode Flash controller mode must pass value 0 Return Code CMD_SUCCESS followed by 32 bit flash signature in decimal format When CRP1 is enabled the signature is read for the entire flash ADDR_NOT_MAPPED PARAM_ERROR Description This command is used to r...

Page 36: ...amming is completed successfully Table 36 ISP IAP Error codes Return Code Error code Description 0x0 CMD_SUCCESS Command is executed successfully Sent by ISP handler only when command given by the host has been completely and successfully executed 0x1 INVALID_COMMAND Invalid command 0x2 SRC_ADDR_ERROR Source address is not on word boundary 0x3 DST_ADDR_ERROR Destination address is not on a correct...

Page 37: ...T Invalid stop bit setting 0x13 CODE_READ_ PROTECTION_ENABLED Code read protection enabled 0x14 Reserved 0x15 USER_CODE_CHECKSUM User code checksum is invalid 0x16 Reserved 0x17 EFRO_NO_POWER FRO not turned on in the PDRUNCFG register 0x18 FLASH_NO_POWER Flash not turned on in the PDRUNCFG register 0x19 Reserved 0x1A Reserved 0x1B FLASH_NO_CLOCK Flash clock disabled in the AHBCLKCTRL register 0x1C...

Page 38: ...t is thumb code therefore called as 0x0F001FF1 by the Cortex M4 to insure Thumb operation The IAP function could be called in the following way using C Define the IAP location entry point Since the least significant bit of the IAP location is set there will be a change to Thumb instruction set if called by the Cortex M4 Define data structure or pointers to pass IAP command table and result table t...

Page 39: ...y IAP Command Command code Section Prepare sector s for write operation 50 decimal 5 6 1 Copy RAM to flash 51 decimal 5 6 2 Erase sector s 52 decimal 5 6 3 Blank check sector s 53 decimal 5 6 4 Read Part ID 54 decimal 5 6 5 Read Boot code version 55 decimal 5 6 6 Compare 56 decimal 5 6 7 Reinvoke ISP 57 decimal 5 6 8 Read UID 58 decimal 5 6 9 Erase page s 59 decimal 5 6 10 Read Signature 73 decima...

Page 40: ...e same Start and End sector numbers Table 39 IAP Copy RAM to flash command Command Copy RAM to flash Input Command code 51 decimal Param0 DST Destination flash address where data bytes are to be written This address should be a 64 byte boundary Param1 SRC Source RAM address from which data bytes are to be read This address should be a word boundary Param2 Number of bytes to be written Should be 64...

Page 41: ...s Remark All user code must be written in such a way that no master accesses the flash while this command is executed and the flash is erased Table 41 IAP Blank check sector s command Command Blank check sector s Input Command code 53 decimal Param0 Start Sector Number Param1 End Sector Number should be greater than or equal to start sector number Status code CMD_SUCCESS BUSY SECTOR_NOT_BLANK INVA...

Page 42: ...multiple of 4 Status code CMD_SUCCESS COMPARE_ERROR COUNT_ERROR Byte count is not a multiple of 4 ADDR_ERROR ADDR_NOT_MAPPED Result Result0 Offset of the first mismatch if the status code is COMPARE_ERROR Description This command is used to compare the memory contents at two locations Table 45 Reinvoke ISP Command Compare Input Command code 57 decimal Param0 mode ISP interface selection 0 Auto or ...

Page 43: ...MD_SUCCESS BUSY SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION INVALID_PAGE Result None Description This command is used to erase a page or multiple pages of on chip flash memory To erase a single page use the same start and end page numbers Remark All user code must be written in such a way that no master accesses the flash while this command is executed and the flash is erased Table 48 IAP Read Signatu...

Page 44: ...and code 80 decimal Param0 FAIM page number Param1 Memory address to store the value read from FAIM Status code CMD_SUCCESS ADDR_NOT_MAPPED Result None Description This command reads a given page of FAIM into the memory provided Table 50 IAP Write FAIM page command Command Write FAIM page Input Command code 81 decimal Param0 FAIM page number Param1 Pointer to the memory address holding data to be ...

Page 45: ...e sends the first probe command via I2C or SPI interface and it is accepted by the LPC84x then the interface is detected the ISP pin switches to an output high as ISP_IRQ When the FAIM configuration is valid and interface selection is either I2C or SPI ISP mode this pin switches to an output high immediately without a probe message When using the Reinvoke ISP command the host interface is selected...

Page 46: ... SSEL to first clock timing should not be less than 100uS SPI transfer configuration should be SPI Mode 0 with 8 data bits SPI transactions are bi directional During the command packet phase the host system should ignore the read data send data from LPC84x During the response phase the LPC84x will ignore the read data send data from host Although SPI is bi directional the command and response pack...

Page 47: ...mand to get back into the I2C SPI ISP mode Table 51 ISP commands allowed for different CRP levels ISP command CRP disabled CRP1 CRP2 CRP3 no entry in ISP mode allowed SH_CMD_GET_VERSION yes yes yes n a SH_CMD_RESET yes yes yes n a SH_CMD_BOOT yes yes yes n a SH_CMD_CHECK_IMAGE yes yes yes n a SH_CMD_PROBE yes yes yes n a SH_CMD_WRITE_BLOCK yes yes not sector 0 no n a SH_CMD_READ_BLOCK yes no no n ...

Page 48: ...xA1 5 8 1 Reset device 0xA2 5 8 2 Boot image 0xA3 5 8 3 Check image 0xA4 5 8 4 Probe 0xA5 5 8 5 Write block 0xA6 5 8 6 Read block 0xA7 5 8 7 Sector erase 0xA8 5 8 8 Page erase 0xA9 5 8 9 Page write 0xAA 5 8 10 Page read 0xAB 5 8 11 Write sub block 0xAC 5 8 12 Read sub block 0xAD 5 8 13 Bulk erase 0xAE 5 8 14 Write RAM 0xB0 5 8 15 GOTO 0xB1 5 8 16 FAIM read 0xBE 5 8 17 FAIM write 0xBF 5 8 18 Table ...

Page 49: ...I2C or SPI interface when in auto detection mode This command is required when booting into the I2C SPI ISP mode from a reset condition The probe command data is accepted on the supported I2C or SPI Table 55 Command packet Field Offset Size bytes Value Description command 0x0 0x1 0xA2 Reset command identifier Table 56 Command packet Field Offset Size bytes Value Description command 0x0 0x1 0xA3 Bo...

Page 50: ...is used to write a block of data to flash A block of data is 128 bytes Table 60 Command packet Field Offset Size bytes Value Description command 0x0 0x1 0xA5 Probe command identifier ifSel 0x1 0x1 Host interface type and port Must match selected interface used to the LPC84x 1 I2C0 port 4 SPI0 port Reserved0 0x2 0x1 Set to 0x00 Reserved1 0x3 0x1 Set to 0x00 Reserved2 0x4 0x1 Set to 0x00 Reserved3 0...

Page 51: ...cess Field Offset Size bytes Value Description sop 0x0 0x1 0x55 Start of packet identifier command 0x1 0x1 0xA6 Processed command identifier length 0x2 0x2 0x00 On success this field is set to 0 Table 65 Response packet error Field Offset Size bytes Value Description sop 0x0 0x1 0x55 Start of packet identifier command 0x1 0x1 0xA6 Processed command identifier length 0x2 0x2 0x00 On error this fiel...

Page 52: ...lash sector number to be erased For example to erase flash sector at 0x2000 this parameter should be set to 8 Table 70 Response packet success Field Offset Size bytes Value Description sop 0x0 0x1 0x55 Start of packet identifier command 0x1 0x1 0xA8 Processed command identifier length 0x2 0x2 0x00 On success this field is set to 0 Table 71 Response packet error Field Offset Size bytes Value Descri...

Page 53: ...C field for this packet pageNum 0x2 0x2 Flash page number in which the appended data to be programmed For example to program flash page at 0x8000 this parameter should be set to 512 data 0x4 Page_size Data to be programmed in flash checkSum Page_size 4 0x4 CRC32 CRC32 of the packet excluding this field Set this field to 0 if crcCheck is set to 1 Table 76 Response packet success Field Offset Size b...

Page 54: ...size 4 On success this field is set to Page_size 4 data 0x4 Page_size Flash page content checkSum Page_size 4 0x4 CRC32 CRC32 of the packet excluding this field Table 80 Response packet error Field Offset Size bytes Value Description sop 0x0 0x1 0x55 Start of packet identifier command 0x1 0x1 0xAB Processed command identifier length 0x2 0x2 0x04 On error this field is set to 4 errorCode 0x4 0x4 Er...

Page 55: ... h parameters Table 84 Command packet Field Offset Size bytes Value Description command 0x0 0x1 0xAD Read subblock command identifier subBlock 0x1 0x1 Bit 0 If set CRC check is not done for this packet Bits 5 1 Specifies the sub block number Bits 7 6 Specifies the sub block size 00 32 bytes 01 64 bytes 10 reserved 11 reserved blockNum 0x2 0x2 Flash block number to read For example to read sub bloc...

Page 56: ... 89 Response packet error Field Offset Size bytes Value Description sop 0x0 0x1 0x55 Start of packet identifier command 0x1 0x1 0xAE Processed command identifier length 0x2 0x2 0x4 On error this field is set to 4 errorCode 0x4 0x4 Error code Error code specified in error h parameters Table 90 Command packet Field Offset Size bytes Value Description command 0x0 0x1 0xB0 Write RAM command identifier...

Page 57: ...ode specified in error h parameters Table 93 Command packet Field Offset Size bytes Value Description command 0x0 0x1 0xB1 GoTo command identifier address 0x4 0x4 Code address to jump to user code Table 94 Response packet error Field Offset Size bytes Value Description sop 0x0 0x1 0x55 Start of packet identifier command 0x1 0x1 0xB1 Processed command identifier length 0x2 0x2 0x4 Length of the res...

Page 58: ...x55 Start of packet identifier command 0x1 0x1 0xBE Processed command identifier length 0x2 0x2 0x4 Length of the response packet 0x4 failure errorCode 0x4 0x4 Error code Error code specified in error h Table 98 Command packet Field Offset Size bytes Value Description command 0x0 0x1 0xBF FAIM write command identifier crcCheck 0x1 0x1 00 Do CRC check for this packet 01 Ignore CRC field for this pa...

Page 59: ...ta length not including this header CmdResponse_t Structure describing Read Write block command packet format typedef struct uint8_t cmd Command ID uint8_t crc_check specifies if we need to do CRC check before processing uint16_t block_nr Block number uint32_t data SL_FLASH_BLOCK_SZ 4 Data uint32_t crc32 CRC32 of command header and data CmdRWBlockParam_t Structure describing Read Write page comman...

Page 60: ...be zero uint16_t sec_nr Sector number CmdEraseSectorParam_t Structure describing Bulk erase command packet format typedef struct uint8_t cmd Command ID uint8_t reserved Should be zero uint8_t start_sec Start Sector number uint8_t end_sec End Sector number CmdBulkEraseParam_t Structure describing response packet with data typedef struct CmdResponse_t hdr Response header uint32_t data SL_FLASH_BLOCK...

Page 61: ...01 Register overview FMC base address 0x4004 0000 Name Access Address offset Description Reset value Reference FLASHCFG R W 0x010 Flash configuration register Section 6 4 1 FMSSTART R W 0x020 Signature start address register 0 Section 6 4 2 FMSSTOP R W 0x024 Signature stop address register 0 Section 6 4 3 FMSW0 R 0x02C Signature word Section 6 4 4 FMSTAT R 0xFE0 Signature generation status registe...

Page 62: ...TAT SIG_DONE should be cleared via the FMSTATCLR register before starting a signature generation operation otherwise the status might indicate completion of a previous operation Table 103 Flash Module Signature Start register FMSSTART 0x4004 0020 bit description Bit Symbol Description Reset value 16 0 START Signature generation start address corresponds to AHB byte address bits 18 2 0 31 17 Reserv...

Page 63: ...iption Reset value 1 0 Reserved Read value is undefined only zero should be written NA 2 SIG_DONE When 1 a previously started signature generation has completed See FMSTATCLR register description for clearing this flag 0 31 2 Reserved Read value is undefined only zero should be written NA Table 107 Flash module signature status clear register FMSTATCLR offset 0x0FE8 bit description Bit Symbol Desc...

Page 64: ...eneration is defined by writing the start address to the signature start address register FMSSTART and the stop address to the signature stop address register FMSSTOP The start and stop addresses must be aligned to 32 bit boundaries Signature generation is started by setting the STRTBIST bit in the FMSSTOP register Setting the STRTBIST bit is typically combined with the signature stop address in a...

Page 65: ... The 32 bit signature reflects the corrected data read from the flash and the flash parity bits and check bit values 6 5 1 3 Content verification The signature as it is read from the FMSW0 register must be equal to the reference signature The following pseudo code shows the algorithm to derive the reference signature sign 0 FOR address FMSSTART START to FMSSTOP STOPA FOR i 0 TO 30 nextSign i f_Q a...

Page 66: ...ntroller NVIC is an integral part of the Cortex M0 The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts 7 3 1 Interrupt sources Table 108 lists the interrupt sources for each peripheral function Each peripheral device may have one or more interrupt lines to the Vectored Interrupt Controller Each line may represent more than one interru...

Page 67: ...description 9 SCT_IRQ State configurable timer interrupt EVFLAG SCT event 10 MRT_IRQ Multi rate timer interrupt Global MRT interrupt GFLAG0 GFLAG1 GFLAG2 GFLAG3 11 CMP_IRQ Analog comparator interrupt COMPEDGE rising falling or both edges can set the bit 12 WDT_IRQ Windowed watchdog timer interrupt WARNINT watchdog warning interrupt 13 BOD_IRQ BOD interrupts BODINTVAL BOD interrupt level 14 FLASH_I...

Page 68: ...te to the VTOR register in the NVIC to relocate the vector table start address to a different memory location For a description of the VTOR register see the ARM Cortex M0 documentation Ref 3 24 PININT0_IRQ Pin interrupt 0 or pattern match engine slice 0 interrupt PSTAT pin interrupt status 25 PININT1_IRQ Pin interrupt 1 or pattern match engine slice 1 interrupt PSTAT pin interrupt status 26 PININT...

Page 69: ...ctive state for specific peripheral functions 0 Table 114 0x304 Reserved 0 IPR0 RW 0x400 Interrupt Priority Registers 0 This register allows assigning a priority to each interrupt This register contains the 2 bit priority fields for interrupts 0 to 3 0 Table 115 IPR1 RW 0x404 Interrupt Priority Registers 1 This register allows assigning a priority to each interrupt This register contains the 2 bit...

Page 70: ..._DAC0 Interrupt enable 0 3 ISE_UART0 Interrupt enable 0 4 ISE_UART1 Interrupt enable 0 5 ISE_UART2 Interrupt enable 0 6 Reserved 0 7 ISE_I2C1 Interrupt enable 0 8 ISE_I2C0 Interrupt enable 0 9 ISE_SCT Interrupt enable 0 10 ISE_MRT Interrupt enable 0 11 ISE_CMP Interrupt enable for comparator 0 12 ISE_WDT Interrupt enable 0 13 ISE_BOD Interrupt enable 0 14 ISE_FLASH Interrupt enable 0 15 ISE_WKT In...

Page 71: ...l Description Reset value 0 ICE_SPI0 Interrupt disable 0 1 ICE_SPI1 Interrupt disable 0 2 ICE_DAC0 Interrupt disable 0 3 ICE_UART0 Interrupt disable 0 4 ICE_UART1 Interrupt disable 0 5 ICE_UART2 Interrupt disable 0 6 Reserved 0 7 ICE_I2C1 Interrupt disable 0 8 ICE_I2C0 Interrupt disable 0 9 ICE_SCT Interrupt disable 0 10 ICE_MRT Interrupt disable 0 11 ICE_CMP Interrupt disable for comparator 0 12 ...

Page 72: ...t disable for both pinint7 and USART4 0 Table 111 Interrupt clear enable register 0 ICER0 address 0xE000 E180 continued Bit Symbol Description Reset value Table 112 Interrupt set pending register 0 register ISPR0 address 0xE000 E200 bit description Bit Symbol Description Reset value 0 ISP_SPI0 Interrupt pending set 0 1 ISP_SPI1 Interrupt pending set 0 2 ISP_DAC0 Interrupt pending set 0 3 ISP_UART0...

Page 73: ...errupt pending set for both pinint5 and DAC1 0 30 ISP_PININT6 or ISP_UART3 Interrupt pending set for both pinint6 and USART3 0 31 ISP_PININT7 or ISP_USART4 Interrupt pending set for both pinint7 and USART4 0 Table 112 Interrupt set pending register 0 register ISPR0 address 0xE000 E200 bit description continued Bit Symbol Description Reset value Table 113 Interrupt clear pending register 0 register...

Page 74: ...ending clear 0 25 ICP_PININT1 Interrupt pending clear 0 26 ICP_PININT2 Interrupt pending clear 0 27 ICP_PININT3 Interrupt pending clear 0 28 ICP_PININT4 Interrupt pending clear 0 29 ICP_PININT5 or ICP_DAC1 Interrupt pending clear for both pinint5 and DAC1 0 30 ICP_PININT6 or ICP_USART3 Interrupt pending clear for both pinint6 and USART3 0 31 ICP_PININT7 or ICP_USART4 Interrupt pending clear for bo...

Page 75: ...ctive 0 27 IAB_PININT3 Interrupt active 0 28 IAB_PININT4 Interrupt active 0 29 IAB_PININT5 or IAB_DAC1 Interrupt active for both pinint5 and DAC1 0 30 IAB_PININT6 or IAB_USART3 Interrupt active for both pinint6 and USART3 0 31 IAB_PININT7 or IAB_USART4 Interrupt active for both pinint7 and USART4 0 Table 114 Interrupt Active Bit Register 0 IABR0 address 0xE000 E300 bit description continued Bit Sy...

Page 76: ...e 116 Interrupt Priority Register 1 IPR1 address 0xE000 E404 bit description Bit Symbol Description Table 117 Interrupt Priority Register 2 IPR2 address 0xE000 E408 bit description Bit Symbol Description 5 0 These bits ignore writes and read as 0 7 6 IP_I2C0 Interrupt Priority 0 highest priority 3 lowest priority 13 8 These bits ignore writes and read as 0 15 14 IP_SCT Interrupt Priority 0 highest...

Page 77: ...ity 21 16 These bits ignore writes and read as 0 23 22 IP_ADC_THCMP Interrupt Priority 0 highest priority 3 lowest priority 29 24 These bits ignore writes and read as 0 31 30 IP_ADC_OVR Interrupt Priority 0 highest priority 3 lowest priority Table 120 Interrupt Priority Register 5 IPR5 address 0xE000 E414 bit description Bit Symbol Description 5 0 These bits ignore writes and read as 0 7 6 IP_DMA ...

Page 78: ...ription Bit Symbol Description 5 0 These bits ignore writes and read as 0 7 6 IP_PININT4 Interrupt Priority 0 highest priority 3 lowest priority 13 8 These bits ignore writes and read as 0 15 14 IP_PININT5 or IP_DAC1 Interrupt Priority 0 highest priority 3 lowest priority 21 16 These bits ignore writes and read as 0 23 22 IP_PININT6 or IP_USART3 Interrupt Priority 0 highest priority 3 lowest prior...

Page 79: ...control BOD configuration MTB trace start and stop Interrupt latency control Select a source for the NMI Calibrate system tick timer 8 3 Basic configuration Configure the SYSCON block as follows The SYSCON uses the CLKIN CLKOUT RESET and XTALIN OUT pins Configure the pin functions through the switch matrix See Section 8 4 No clock configuration is needed The clock to the SYSCON block is always ena...

Page 80: ...ut clock use the PLL to boost the input frequency 1 Power up the system PLL in the PDRUNCFG register Section 8 6 47 Power configuration register 2 Select the PLL input in the SYSPLLCLKSEL register You have the following input options FRO 12 MHz internal oscillator default External clock input It can be external crystal oscillator using the XTALIN XTALOUT pins or CLKIN from external pin Remark The ...

Page 81: ...nd therefore must have an active clock The core is always clocked Section 8 6 21 System clock control 0 register Section 8 6 22 System clock control 1 register 8 3 4 Set up the system oscillator using XTALIN and XTALOUT To use the system oscillator with the LPC84x assign the XTALIN and XTALOUT pins which connect to the external crystal through the fixed pin function in the switch matrix XTALIN and...

Page 82: ...tor used for wake up timing is controlled by the PMU Except for the USART clock SPI clock I2C clock SCTimer PWM clock ADC clock and the clock to configure the glitch filters of the digital I O pins the clocks to the core and peripherals run at the same frequency The maximum system clock frequency is 30 MHz See Figure 7 Remark The main clock frequency is limited to 100 MHz Table 123 SYSCON pin desc...

Page 83: ...ne bit per destination 00 01 10 1 11 main_clk main_clk Divider to AHB peripherals AHB matrix memories etc to CPU fro external_clk wdt_osc_clk fro_div PLL clock select SYSPLLCLKSEL 1 0 00 01 10 1 11 1 fro main_clk sys_pll0_clk none SCT clock select SCTCLKSEL 1 0 00 01 10 11 peripheral_clk Divider pin filter i SCTCLKDIV SYSAHBCLKCTRL0 SCT SCT Clock Divider to SCT input 4 CLKOUTDIV CLKOUT Divider fro...

Page 84: ...fro 00 01 10 11 Fractional Rate Divider 0 FRG0 Fractional Rate Divider 1 FRG1 fro main_clk frg0clk frg1clk SPln clock select SPInCLKSEL 2 0 000 001 010 011 fro_div 100 none 111 SYSAHBCLKCTRL0 SPln One for each SPI SPI0 through SPI1 to SPIn fro main_clk frg0clk frg1clk I2Cn clock select I2CnCLKSEL 2 0 000 001 010 011 fro_div 100 none 111 SYSAHBCLKCTRL0 I2Cn One for each l2C I2C0 through I2C3 to I2C...

Page 85: ... its source selection are shown in Figure 8 UM11029 clock generation continued fro The output of the currently selected on chip FRO oscillator See UM11029 User manual fro_div The FRO output This may be either 15 MH 12 MHz or 9 MHz See UM11029 User manual main_clk The main clock used by the CPU and AHB bus and potentially many others The main clock and its source selection are shown in Figure 7 LPC...

Page 86: ...ystem control block see Section 8 6 42 Pin interrupt select registers 8 6 Register description All system control block registers reside on word address boundaries Details of the registers appear in the description of each function Reset values describe the content of the registers after the bootloader has executed All address offsets shown in Table 125 as reserved should not be written to Table 1...

Page 87: ...ct for UART0 0x7 8 6 25 UART1CLKSEL R W 0x094 Function clock source select for UART1 0x7 8 6 25 UART2CLKSEL R W 0x098 Function clock source select for UART2 0x7 8 6 25 UART3CLKSEL R W 0x09C Function clock source select for UART3 0x7 8 6 25 UART4CLKSEL R W 0x0A0 Function clock source select for UART4 0x7 8 6 25 I2C0CLKSEL R W 0x0A4 Function clock source select for I2C0 0x7 8 6 25 I2C1CLKSEL R W 0x0...

Page 88: ...W 0x148 Peripheral clock 1 to the IOCON block for programmable glitch filter 0 8 6 37 IOCONCLKDIV0 R W 0x14C Peripheral clock 0 to the IOCON block for programmable glitch filter 0 8 6 37 BODCTRL R W 0x150 Brown Out Detect 0 8 6 38 SYSTCKCAL R W 0x154 System tick counter calibration 0 8 6 39 R W 0x158 0x16C Reserved IRQLATENCY R W 0x170 IRQ delay Allows trade off between interrupt latency and deter...

Page 89: ...d then divided down to provide the actual clock used by the CPU peripherals and memories The PLL can produce a clock up to the maximum allowed for the CPU Remark The divider values for P and M must be selected so that the PLL output clock frequency FCLKOUT is lower than 100 MHz 0x218 0x22C Reserved PDSLEEPCFG R W 0x230 Power down states in deep sleep mode 0xFFFF 8 6 45 PDAWAKECFG R W 0x234 Power d...

Page 90: ... value M is the programmed MSEL value 1 00000 Division ratio M 1 to 11111 Division ratio M 32 0 6 5 PSEL Post divider ratio P The division ratio is 2 P 0 0x0 P 1 0x1 P 2 0x2 P 4 0x3 P 8 31 7 Reserved Do not write ones to reserved bits Table 128 System PLL status register SYSPLLSTAT address 0x4004 800C bit description Bit Symbol Value Description Reset value 0 LOCK PLL lock status 0 0 PLL not locke...

Page 91: ...as wdt_osc_clk Fclkana 2 1 DIVSEL 9 3 kHz to 2 3 MHz nominal values Remark Any setting of the FREQSEL bits will yield a Fclkana value within 40 of the listed frequency value The watchdog oscillator is the clock source with the lowest power consumption If accurate timing is required use the FRO or system oscillator Remark The frequency of the watchdog oscillator is undefined after reset The watchdo...

Page 92: ... The FRODIRECTCLKUEN register updates the clock source of the FRO clock with the new input clock after the FROOSCCTRL register bit 17 has been written to In order for the update to take effect first write a zero to the FRODIRECTCLKUEN register and then write a one to FRODIRECTCLKUEN Table 131 FRO oscillator control register FROOSCCTRL address 0x4004 8028 bit description Bit Symbol Value Descriptio...

Page 93: ...e toggled from LOW to HIGH for the update to take effect Table 133 System reset status register SYSRSTSTAT address 0x4004 8038 bit description Bit Symbol Value Description Reset value 0 POR POR reset status 0 0 No POR detected 1 POR detected Writing a one clears this reset 1 EXTRST Status of the external RESET pin External reset status 0 0 No reset event detected 1 Reset detected Writing a one cle...

Page 94: ...d from 0 to 1 for the update to take effect 8 6 12 Main clock PLL source update enable register The MAINCLKPLLUEN register updates the clock source of the main clock with the new input clock after the MAINCLKPLLSEL register has been written to In order for the update to take effect first write a zero to bit 0 of this register then write a one Table 135 System PLL clock source update enable registe...

Page 95: ...er then write a one 8 6 15 System clock divider register This register controls how the main clock is divided to provide the system clock to the core memories and the perispherals The system clock can be shut down completely by setting the DIV field to zero Table 138 Main clock source select register MAINCLKSEL address 0x4004 8050 bit description Bit Symbol Value Description Reset value 1 0 SEL Cl...

Page 96: ...r sys_pll 8 6 19 SCT clock divider register The SCTCLKDIV register controls how the SCT clock is divided to provide the SCT clock to the SCT module The SCT clock can be shut down completely by setting the DIV field to zero Table 141 ADC clock source select register ADCCLKSEL address 0x4004 8064 bit description Bit Symbol Value Description Reset value 1 0 SEL Clock source for ADC clock 0x0 0x0 FRO ...

Page 97: ... SCTCLKDIV address 0x4004 8070 bit description Bit Symbol Value Description Reset value 7 0 DIV SCT clock divider values 0 SCT clock disabled 1 Divide by 1 255 Divide by 255 0x0 31 8 Reserved Table 145 External clock source select register EXTCLKSEL address 0x4004 8074 bit description Bit Symbol Value Description Reset value 0 SEL Clock source for external clock 0x0 0x0 System oscillator 0x1 CLK_I...

Page 98: ...or self wake up timer 0 0 Disable 1 Enable 10 MRT Enables clock for multi rate timer 0 Disable 1 Enable 11 SPI0 Enables clock for SPI0 0 0 Disable 1 Enable 12 SPI1 Enables clock for SPI1 0 Disable 1 Enable 13 CRC Enables clock for CRC 0 0 Disable 1 Enable 14 UART0 Enables clock for USART0 0 0 Disable 1 Enable 15 UART1 Enables clock for USART1 0 0 Disable 1 Enable 16 UART2 Enables clock for USART2 ...

Page 99: ...I2C3 Enables clock to I2C3 0 0 Disable 1 Enable 24 ADC Enables clock to ADC 0 0 Disable 1 Enable 25 CTIMER0 Enables clock for CTIMER0 0 0 Disable 1 Enable 26 MTB Enables clock to micro trace buffer control registers Turn on this clock when using the micro trace buffer for debug purposes 0 0 Disable 1 Enable 27 DAC0 Enable clock for DAC0 0 0 Disable 1 Enable 28 GPIO_INT Enable clock for GPIO pin in...

Page 100: ...SAHBCLKCTRL0 address 0x4004 8080 bit description continued Bit Symbol Value Description Reset value Table 147 System clock control 1 register SYSAHBCLKCTRL1 address 0x4004 8084 bit description Bit Symbol Value Description Reset value 0 Reserved 0 1 DAC1 Enables clock for DAC1 0 0 Disable 1 Enable 31 2 Reserved Table 148 Peripheral reset control 0 register PRESETCTRL0 address 0x4004 8088 bit descri...

Page 101: ... reset 14 UART0_RST_N UART0 reset control 1 0 Assert the UART0 reset 1 Clear the flash UART0 reset 15 UART1_RST_N UART1 reset control 1 0 Assert the UART1 reset 1 Clear the UART1 reset 16 UART2_RST_N UART2 reset control 1 0 Assert the UART2 reset 1 Clear the UART2 reset 17 Reserved 18 IOCON_RST_N IOCON reset control 1 0 Assert the IOCON reset 1 Clear the IOCON reset 19 ACMP_RST_N Analog comparator...

Page 102: ...set control 1 0 Assert the CTIMER reset 1 Clear the CTIMER reset 26 Reserved 1 27 DAC0_RST_N DAC0 reset control 1 0 Assert the DAC0 reset 1 Clear the DAC0 reset 28 GPIOINT_RST_N GPIOINT reset control 1 0 Assert the GPIOINT reset 1 Clear the GPIOINT reset 29 DMA_RST_N DMA reset control 1 0 Assert the DMA reset 1 Clear the DMA reset 30 UART3_RST_N UART3 reset control 1 0 Assert the UART3 reset 1 Cle...

Page 103: ...er 8 LPC84x System configuration SYSCON 3 FRG0_RST_N Fractional baud rate generator 0 reset control 1 0 Assert the FRG0 reset 1 Clear the FRG0 reset 4 FRG1_RST_N Fractional baud rate generator 1 reset control 1 0 Assert the FRG1 reset 1 Clear the FRG1 reset 31 5 Reserved 1 Table 149 Peripheral reset control 1 register PRESETCTRL1 address 0x4004 808C bit description Bit Symbol Value Description Res...

Page 104: ...A8 I2C2 clock source select register I2C2CLKSEL address 0x4004 80AC I2C3 clock source select register I2C3CLKSEL address 0x4004 80AC SPI0 clock source select register SPI0CLKSEL address 0x4004 80B4 SPI1 clock source select register SPI1CLKSEL address 0x4004 80B8 8 6 26 Fractional generator 0 divider value register The UART I2C SPI clock come from the FCLK multiplexer The FRGCLK0 is one clock sourc...

Page 105: ...c_clk 1 MULT DIV FRG0_SRC_CLK is input clock of fractional generator 0 which can be the FRO main clock or sys pll clock The fractional portion 1 MULT DIV is determined by the two fractional divider registers in the SYSCON block The DIV denominator of the fractional divider value is programmed in the FRG0DIV register See Table 151 The MULT value programmed in this register is the numerator of the f...

Page 106: ...tional divider registers in the SYSCON block The DIV value programmed in this register is the denominator of the divider used by the fractional rate generator to create the fractional component of FRG1CLK The MULT value of the fractional divider is programmed in the FRG1MULT register See Table 155 Remark To use the fractional baud rate generator you must write 0xFF to this register to yield a deno...

Page 107: ...ed in the FRG1DIV register See Table 154 The MULT value programmed in this register is the numerator of the fractional divider value used by the fractional rate generator to create the fractional component to the baud rate See also Section 17 3 1 Configure the USART clock and baud rate Section 17 7 1 Clocking and baud rates 8 6 31 FRG1 clock source select register The FRG1CLKSEL register selects t...

Page 108: ...ock source select register FRG1CLKSEL address 0x4004 80E8 bit description Bit Symbol Value Description Reset value 1 0 SEL Clock source for FRG1_SRC clock 0x0 0x0 FRO 0x1 Main clock 0x2 SYS PLL 0x3 None 31 2 Reserved Table 157 CLKOUT clock source select register CLKOUTSEL address 0x4004 80F0 bit description Bit Symbol Value Description Reset value 2 0 SEL CLKOUT clock source 7 0x0 FRO 0x1 Main clo...

Page 109: ...ndividually configure the seven peripheral input clocks IOCONFILTR_PCLK to the IOCON programmable glitch filter The clocks can be shut down by setting the DIV bits to 0x0 Table 159 External trace buffer command register EXTTRACECMD address 0x4004 80FC bit description Bit Symbol Description Reset value 0 START Trace start command Writing a one to this bit sets the TSTART signal to the MTB to HIGH a...

Page 110: ...his register determines the value of the SYST_CALIB register Table 162 IOCON glitch filter clock divider registers 6 to 0 IOCONCLKDIV 6 0 address 0x4004 8134 IOCONCLKDIV6 to 0x004 814C IOCONFILTCLKDIV0 bit description Bit Symbol Description Reset value 7 0 DIV IOCON glitch filter clock divider values 0 Disable IOCONFILTR_PCLK 1 Divide by 1 255 Divide by 255 0 31 8 Reserved 0x00 Table 163 BOD contr...

Page 111: ...rminism will depend on the application The default setting for this register is 0x010 8 6 41 NMI source selection register The NMI source selection register selects a peripheral interrupt as source for the NMI interrupt of the ARM Cortex M0 core For a list of all peripheral interrupts and their IRQ numbers see Table 108 For a description of the NMI functionality see Section 7 3 2 Remark When you w...

Page 112: ...nterrupts must be enabled in the NVIC using interrupt slots 24 to 31 see Table 108 To use the selected pins for pin interrupts or the pattern match engine see Section 13 5 2 Pattern match engine 8 6 43 Start logic 0 pin wake up enable register The STARTERP0 register enables the selected pin interrupts for wake up from deep sleep mode and power down modes Remark Also enable the corresponding interr...

Page 113: ...led 4 PINT4 GPIO pin interrupt 4 wake up 0 0 Disabled 1 Enabled 5 PINT5 GPIO pin interrupt 5 wake up 0 0 Disabled 1 Enabled 6 PINT6 GPIO pin interrupt 6 wake up 0 0 Disabled 1 Enabled 7 PINT7 GPIO pin interrupt 7 wake up 0 0 Disabled 1 Enabled 31 8 Reserved Table 168 Start logic 0 pin wake up enable register 0 STARTERP0 address 0x4004 8204 bit description continued Bit Symbol Value Description Res...

Page 114: ...p 0 0 Disabled 1 Enabled 8 I2C0 I2C0 interrupt wake up 0 0 Disabled 1 Enabled 11 9 Reserved 0 12 WWDT WWDT interrupt wake up 0 0 Disabled 1 Enabled 13 BOD BOD interrupt wake up 0 0 Disabled 1 Enabled 14 Reserved 15 WKT Self wake up timer interrupt wake up 0 0 Disabled 1 Enabled 20 16 Reserved 21 I2C2 I2C2 interrupt wake up 0 0 Disabled 1 Enabled 22 I2C3 I2C3 interrupt wake up 0 0 Disabled 1 Enable...

Page 115: ...for details 8 6 46 Wake up configuration register This register controls the power configuration of the device when waking up from Deep sleep or Power down mode Table 170 Deep sleep configuration register PDSLEEPCFG address 0x4004 8230 bit description Bit Symbol Value Description Reset value 2 0 Reserved 0b111 3 BOD_PD BOD power down control for Deep sleep and Power down mode 1 0 Powered 1 Powered...

Page 116: ...ke up configuration 1 0 Powered 1 Powered down 6 WDTOSC_PD Watchdog oscillator wake up configuration Changing this bit to powered down has no effect when the LOCK bit in the WWDT MOD register is set In this case the watchdog oscillator is always running 1 0 Powered 1 Powered down 7 SYSPLL_PD System PLL wake up configuration 1 0 Powered 1 Powered down 9 8 Reserved Always write these bits as 0b01 0b...

Page 117: ...UNCFG address 0x4004 8238 bit description Bit Symbol Value Description Reset value 0 FROOUT_PD FRO oscillator output power 0 0 Powered 1 Powered down 1 FRO_PD FRO oscillator power down 0 0 Powered 1 Powered down 2 FLASH_PD Flash power down 0 0 Powered 1 Powered down 3 BOD_PD BOD power down 1 0 Powered 1 Powered down 4 ADC_PD ADC wake up configuration 1 0 Powered 1 Powered down 5 SYSOSC_PD Crystal ...

Page 118: ...tion When the internal Reset is removed the processor begins executing at address 0 which is initially the Reset vector mapped from the boot block At that point all of the processor and peripheral registers have been initialized to predetermined values 8 7 2 Brown out detection The brown out detection circuit includes up to three levels for monitoring the voltage on the VDD pin If this voltage fal...

Page 119: ... can be enabled for interrupt in the Interrupt Enable Register in the NVIC see Table 109 in order to cause a CPU interrupt if not software can monitor the signal by reading a dedicated status register If the BOD interrupt is enabled in the STARTERP1 register see Table 169 and in the NVIC the BOD interrupt can wake up the chip from Deep sleep and power down mode If the BOD reset is enabled the forc...

Page 120: ...ck The output signal of the phase frequency detector is also monitored by the lock detector to signal when the PLL has locked on to the input clock Remark The divider values for P and M must be selected so that the PLL output clock frequency FCLKOUT is lower than 30 MHz because the main clock is limited to a maximum frequency of 30 MHz 8 7 3 1 Lock detector The lock detector measures the phase dif...

Page 121: ...127 This guarantees an output clock with a 50 duty cycle 8 7 3 3 2 Feedback divider The feedback divider s division ratio is controlled by the MSEL bits The division ratio between the PLL s output clock and the input clock is the decimal value on MSEL bits plus one as specified in Table 127 8 7 3 3 3 Changing the divider values Changing the divider ratio while the PLL is running is not recommended...

Page 122: ...ected so that the PLL output clock frequency FCLKOUT is 30 MHz Table 175 shows how to configure the PLL for a 12 MHz crystal oscillator using the SYSPLLCTRL register Table 127 8 7 3 4 2 PLL Power down mode In this mode the internal current reference will be turned off the oscillator and the phase frequency detector will be stopped and the dividers will enter a reset state While in PLL Power down m...

Page 123: ...rol of FRO output frequency can be configured through a simple call to the ROM The set_fro_frequency API call must be used to the select desired fro_oscout 30 MHz 24 MHz 18 MHz This is performed by executing a function which is pointed by a pointer within the ROM Driver Table Figure 11 shows the pointer structure used to call the set FRO frequency API Remark Disable all interrupts before making ca...

Page 124: ...tine Fig 11 ROM pointer structure 0x0 0x4 0x8 0x10 0xC Device API 1 FRO API function table IAP calls set_fro_frequency aaa 027483 Ptr to IAP 0x0F001FF1 Ptr to ROM Driver table 0x0F001FF8 ROM Driver Table Reserved Reserved Reserved Ptr to Device API Table n Device API n Ptr to Function 0 Ptr to Function 1 Ptr to Function 2 Ptr to Function n Device API 2 Integer Divide routines function table Pointe...

Page 125: ...actory trim value is used See Figure 8 Clock generation continued and Section 6 5 77 FRO Control register for more details to select fro_oscout 30 24 18 MHz or select divided fro_oscout 1 125 MHz 1 5 MHz 1 875 MHz 9 MHz 12 MHz or 15 MHz based on FAIM low power boot value Table 177 shows the set_fro_frequency routine 9 4 1 1 Param0 frequency The frequency is the required fro_oscout 30 MHz 24 MHz or...

Page 126: ...pin assignment registers After the switch matrix is configured disable the clock to the switch matrix block in the SYSAHBCLKCTRL register Before activating a peripheral or enabling its interrupt use the switch matrix to connect the peripheral to external pins The serial wire debug pins SWDIO and SWCLK are enabled by default on pins PIO0_2 and PIO0_3 Remark For the purpose of programming the pin fu...

Page 127: ... pin x on the LPC84x package to connect the pin function to 3 Use the pin description table to find the default GPIO function PIO0_n or PIO1_ n 32 assigned to package pin x m is the pin number 4 Locate the pin assignment register for the function FUNC in the switch matrix register description 5 Disable any special functions on pin PIO0_n in the PINENABLE0 register or PIO1_ n 32 in the PINENABLE1 r...

Page 128: ...not in the table of movable functions do the following a Locate the function in the pin description table in the data sheet This shows the package pin for this function b Enable the function in the PINENABLE0 PINENABLE1 register All other possible functions on this pins are now disabled 10 3 3 Changing the pin function assignment Pin function assignments can be changed on the fly from one peripher...

Page 129: ... pin These functions are called movable functions A few functions like the crystal oscillator pins XTALIN XTALOUT or the analog comparator inputs can only be assigned to one particular external pin with the appropriate electrical characteristics These functions are called fixed pin functions If a fixed pin function is not used it can be replaced by any other movable function For fixed pin analog f...

Page 130: ...tch matrix the GPIO output becomes disabled Enabling any analog fixed pin function disables all digital functions on the same pin Enabling any digital fixed pin function disables all analog pin function on the same pin Digital and analog functions cannot share the same pin 10 4 1 Movable functions Table 178 Movable functions assign to pins PIO0_0 to PIO0_31 and PIO1_0 to PIO1_21 through switch mat...

Page 131: ...O SCT output 2 PINASSIGN8 Table 188 SCT_OUT3 O SCT output 3 PINASSIGN8 Table 188 SCT_OUT4 O SCT output 4 PINASSIGN8 Table 188 SCT_OUT5 O SCT output 5 PINASSIGN9 Table 189 SCT_OUT6 O SCT output 6 PINASSIGN9 I2C1_SDA I O I2C1 bus data input output PINASSIGN9 Table 189 I2C1_SCL I O I2C1 bus clock input output PINASSIGN9 Table 189 I2C2_SDA I O I2C2 bus data input output PINASSIGN10 Table 190 I2C2_SCL ...

Page 132: ...rk You can assign only one digital output function to an external pin at any given time Remark You can assign more than one digital input function to one external pin 2 Fixed pin functions PINENABLE0 to 1 Some functions require pins with special characteristics and cannot be moved to other physical pins Hence these functions are mapped to a fixed port pin Examples of fixed pin functions are the os...

Page 133: ...le functions SPI0_MOSI SPI0_MISO SPI0_SSEL0 SPI0_SSEL1 0xFFFF FFFF Table 184 PINASSIGN5 R W 0x014 Pin assign register 5 Assign movable functions SPI0_SSEL2 SPI0_SSEL3 SPI1_SCK SPI1_MOSI 0xFFFF FFFF Table 185 PINASSIGN6 R W 0x018 Pin assign register 6 Assign movable functions SPI1_MISO SPI1_SSEL0 SPI1_SSEL1 SCT0_IN0 0xFFFF FFFF Table 186 PINASSIGN7 R W 0x01C Pin assign register 7 Assign movable fun...

Page 134: ...atrix base address 0x4000 C000 continued Name Access Offset Description Reset value Reference Table 180 Pin assign register 0 PINASSIGN0 address 0x4000 C000 bit description Bit Symbol Description Reset value 7 0 U0_TXD_O U0_TXD function assignment The value is the pin number to be assigned to this function The following pins are available PIO0_0 0 to PIO0_31 0x1F and from PIO1_0 0x20 to PIO1_21 0x...

Page 135: ...0x1F and from PIO1_0 0x20 to PIO1_21 0x35 0xFF 31 24 U1_RTS_O U1_RTS function assignment The value is the pin number to be assigned to this function The following pins are available PIO0_0 0 to PIO0_31 0x1F and from PIO1_0 0x20 to PIO1_21 0x35 0xFF Table 182 Pin assign register 2 PINASSIGN2 address 0x4000 C008 bit description Bit Symbol Description Reset value 7 0 U1_CTS_I U1_CTS function assignme...

Page 136: ..._0 0x20 to PIO1_21 0x35 0xFF 31 24 SPI0_SCK_IO SPI0_SCK function assignment The value is the pin number to be assigned to this function The following pins are available PIO0_0 0 to PIO0_31 0x1F and from PIO1_0 0x20 to PIO1_21 0x35 0xFF Table 184 Pin assign register 4 PINASSIGN4 address 0x4000 C010 bit description Bit Symbol Description Reset value 7 0 SPI0_MOSI_IO SPI0_MOSI function assignment The...

Page 137: ... PIO1_0 0x20 to PIO1_21 0x35 0xFF 31 24 SPI1_MOSI_IO SPI1_MOSI function assignment The value is the pin number to be assigned to this function The following pins are available PIO0_0 0 to PIO0_31 0x1F and from PIO1_0 0x20 to PIO1_21 0x35 0xFF Table 186 Pin assign register 6 PINASSIGN6 address 0x4000 C018 bit description Bit Symbol Description Reset value 7 0 SPI1_MISO_IO SPI1_MISO function assignm...

Page 138: ... 0 to PIO0_31 0x1F and from PIO1_0 0x20 to PIO1_21 0x35 0xFF 31 24 SCT_OUT0_O SCT_OUT0 function assignment The value is the pin number to be assigned to this function The following pins are available PIO0_0 0 to PIO0_31 0x1F and from PIO1_0 0x20 to PIO1_21 0x35 0xFF Table 188 Pin assign register 8 PINASSIGN8 address 0x4000 C020 bit description Bit Symbol Description Reset value 7 0 SCT_OUT1_O SCT_...

Page 139: ...nd from PIO1_0 0x20 to PIO1_21 0x35 0xFF 31 24 I2C1_SCL_IO I2C1_SCL function assignment The value is the pin number to be assigned to this function The following pins are available PIO0_0 0 to PIO0_31 0x1F and from PIO1_0 0x20 to PIO1_21 0x35 0xFF Table 190 Pin assign register 10 PINASSIGN10 address 0x4000 C028 bit description Bit Symbol Description Reset value 7 0 I2C2_SDA_IO I2C1_SDA function as...

Page 140: ... 0x1F and from PIO1_0 0x20 to PIO1_21 0x35 0xFF 31 24 UART3_TXD UART3_TXD function assignment The value is the pin number to be assigned to this function The following pins are available PIO0_0 0 to PIO0_31 0x1F and from PIO1_0 0x20 to PIO1_21 0x35 0xFF Table 192 Pin assign register 12 PINASSIGN12 address 0x4000 C030 bit description Bit Symbol Description Reset value 7 0 UART3_RXD UART3_RXD functi...

Page 141: ...The value is the pin number to be assigned to this function The following pins are available PIO0_0 0 to PIO0_31 0x1F and from PIO1_0 0x20 to PIO1_21 0x35 0xFF Table 194 Pin assign register 14 PINASSIGN14 address 0x4000 C038 bit description Bit Symbol Description Reset value 7 0 T0_MAT3 T0_MAT3 function assignment The value is the pin number to be assigned to this function The following pins are a...

Page 142: ...ed on pin PIO0_3 1 SWCLK disabled 6 SWDIO SWDIO function select 0 0 SWDIO enabled on pin PIO0_2 1 SWDIO disabled 7 XTALIN XTALIN function select 1 0 XTALIN enabled on pin PIO0_8 1 XTALIN disabled 8 XTALOUT XTALOUT function select 1 0 XTALOUT enabled on pin PIO0_9 1 XTALOUT disabled 9 RESETN RESETN function select 0 0 RESETN enabled on pin PIO0_5 1 RESETN disabled 10 CLKIN CLKIN function select 1 0...

Page 143: ... pin PIO0_22 1 ADC_4 disabled 19 ADC_5 ADC_5 function select 1 0 ADC_5 enabled on pin PIO0_21 1 ADC_5 disabled 20 ADC_6 ADC_6 function select 1 0 ADC_6 enabled on pin PIO0_20 1 ADC_6 disabled 21 ADC_7 ADC_7 function select 1 0 ADC_7 enabled on pin PIO0_19 1 ADC_7 disabled 22 ADC_8 ADC_8 function select 1 0 ADC_8 enabled on pin PIO0_18 1 ADC_8 disabled 23 ADC_9 ADC_9 function select 1 0 ADC_9 enabl...

Page 144: ...5 NXP Semiconductors UM11029 Chapter 10 LPC84x Switch matrix SWM Remark In analog mode the internal pull up must be disabled via the IOCON register 27 DACOUT1 DACOUT1 function select 1 0 DACOUT1 enabled on pin PIO0_29 1 DACOUT1 disabled 31 28 Reserved 1 Table 195 Pin enable register 0 PINENABLE0 address 0x4000 C1C0 bit description Bit Symbol Value Description Reset value ...

Page 145: ...n mode Three I2Cs support data rates up to 400 kbit s on standard digital pins 11 3 Basic configuration Enable the clock to the IOCON in the SYSAHBCLKCTRL register Table 146 bit 18 Once the pins are configured you can disable the IOCON clock to conserve power Remark If the open drain pins PIO0_10 and PIO0_11 are not available on the package prevent the pins from internally floating as follows Set ...

Page 146: ...block or enable a special function like an analog input on a specific pin Related links Table 178 Movable functions assign to pins PIO0_0 to PIO0_31 and PIO1_0 to PIO1_21 through switch matrix 11 4 3 Pin mode The MODE bit in the IOCON register allows enabling or disabling an on chip pull up resistor for each pin Fig 14 Pin configuration PIN VDD VDD ESD VSS ESD strong pull up strong pull down VDD w...

Page 147: ...rix automatically configures the pin in analog mode whenever an analog input or output is selected as the pin s function In analog mode the internal pull up should be disabled via IOCON register 11 4 6 I2C bus mode The I2C bus pins PIO0_10 and PIO0_11 can be programmed to support a true open drain mode independently of whether the I2C function is selected or another digital function If the I2C fun...

Page 148: ...p enabled in the MODE field Table 197 Register overview I O configuration base address 0x4004 4000 Name Access Address offset Description Reset value Reference PIO0_17 R W 0x000 I O configuration for pin PIO0_17 ADC_9 DACOUT0 FAIM value dependent Table 199 PIO0_13 R W 0x004 I O configuration for pin PIO0_13 ADC_10 FAIM value dependent Table 200 PIO0_12 R W 0x008 I O configuration for pin PIO0_12 F...

Page 149: ...ration for pin PIO1_8 FAIM value dependent Table 228 PIO1_9 R W 0x080 I O configuration for pin PIO1_9 FAIM value dependent Table 229 PIO1_12 R W 0x084 I O configuration for pin PIO1_12 FAIM value dependent Table 230 PIO1_13 R W 0x088 I O configuration for pin PIO1_13 FAIM value dependent Table 231 PIO0_31 R W 0x08C I O configuration for pin PIO0_31 FAIM value dependent Table 232 PIO1_0 R W 0x090 ...

Page 150: ... no yes yes Table 205 PIO0_3 0x014 no no yes yes Table 204 PIO0_4 0x010 no yes yes no Table 203 PIO0_5 0x00C no no yes no Table 202 PIO0_6 0x040 no yes yes no Table 214 PIO0_7 0x03C no yes yes no Table 213 PIO0_8 0x038 no yes yes no Table 212 PIO0_9 0x034 no yes yes no Table 211 PIO0_10 0x020 yes no yes no Table 207 PIO0_11 0x01C yes no yes no Table 206 PIO0_12 0x008 no no yes yes Table 201 PIO0_1...

Page 151: ...52 PIO1_11 0x0D8 no no yes no Table 251 PIO1_12 0x084 no no yes no Table 230 PIO1_13 0x088 no no yes no Table 231 PIO1_14 0x09C no no yes no Table 236 PIO1_15 0x0A0 no no yes no Table 237 PIO1_16 0x0B0 no no yes no Table 241 PIO1_17 0x0B4 no no yes no Table 242 PIO1_18 0x0BC no no yes no Table 244 PIO1_19 0x0C0 no no yes no Table 245 PIO1_20 0x0D0 no no yes no Table 249 PIO1_21 0x0D4 no no yes no ...

Page 152: ...cles Input pulses shorter than two filter clocks are rejected 0x3 3 clock cycles Input pulses shorter than three filter clocks are rejected 15 13 CLK_DIV Select peripheral clock divider for input filter sampling clock Value 0x7 is reserved 0 0x0 IOCONCLKDIV0 0x1 IOCONCLKDIV1 0x2 IOCONCLKDIV2 0x3 IOCONCLKDIV3 0x4 IOCONCLKDIV4 0x5 IOCONCLKDIV5 0x6 IOCONCLKDIV6 16 DACMODE DAC mode enable 0 0x0 Disabl...

Page 153: ...filter clock are rejected 0x2 2 clock cycles Input pulses shorter than two filter clocks are rejected 0x3 3 clock cycles Input pulses shorter than three filter clocks are rejected 15 13 CLK_DIV Select peripheral clock divider for input filter sampling clock Value 0x7 is reserved 0 0x0 IOCONCLKDIV0 0x1 IOCONCLKDIV1 0x2 IOCONCLKDIV2 0x3 IOCONCLKDIV3 0x4 IOCONCLKDIV4 0x5 IOCONCLKDIV5 0x6 IOCONCLKDIV6...

Page 154: ... filter clock are rejected 0x2 2 clock cycles Input pulses shorter than two filter clocks are rejected 0x3 3 clock cycles Input pulses shorter than three filter clocks are rejected 15 13 CLK_DIV Select peripheral clock divider for input filter sampling clock Value 0x7 is reserved 0 0x0 IOCONCLKDIV0 0x1 IOCONCLKDIV1 0x2 IOCONCLKDIV2 0x3 IOCONCLKDIV3 0x4 IOCONCLKDIV4 0x5 IOCONCLKDIV5 0x6 IOCONCLKDIV...

Page 155: ...e filter clock are rejected 0x2 2 clock cycles Input pulses shorter than two filter clocks are rejected 0x3 3 clock cycles Input pulses shorter than three filter clocks are rejected 15 13 CLK_DIV Select peripheral clock divider for input filter sampling clock Value 0x7 is reserved 0 0x0 IOCONCLKDIV0 0x1 IOCONCLKDIV1 0x2 IOCONCLKDIV2 0x3 IOCONCLKDIV3 0x4 IOCONCLKDIV4 0x5 IOCONCLKDIV5 0x6 IOCONCLKDI...

Page 156: ...e filter clock are rejected 0x2 2 clock cycles Input pulses shorter than two filter clocks are rejected 0x3 3 clock cycles Input pulses shorter than three filter clocks are rejected 15 13 CLK_DIV Select peripheral clock divider for input filter sampling clock Value 0x7 is reserved 0 0x0 IOCONCLKDIV0 0x1 IOCONCLKDIV1 0x2 IOCONCLKDIV2 0x3 IOCONCLKDIV3 0x4 IOCONCLKDIV4 0x5 IOCONCLKDIV5 0x6 IOCONCLKDI...

Page 157: ...e filter clock are rejected 0x2 2 clock cycles Input pulses shorter than two filter clocks are rejected 0x3 3 clock cycles Input pulses shorter than three filter clocks are rejected 15 13 CLK_DIV Select peripheral clock divider for input filter sampling clock Value 0x7 is reserved 0 0x0 IOCONCLKDIV0 0x1 IOCONCLKDIV1 0x2 IOCONCLKDIV2 0x3 IOCONCLKDIV3 0x4 IOCONCLKDIV4 0x5 IOCONCLKDIV5 0x6 IOCONCLKDI...

Page 158: ... cycle Input pulses shorter than one filter clock are rejected 0x2 2 clock cycles Input pulses shorter than two filter clocks are rejected 0x3 3 clock cycles Input pulses shorter than three filter clocks are rejected 15 13 CLK_DIV Select peripheral clock divider for input filter sampling clock Value 0x7 is reserved 0 0x0 IOCONCLKDIV0 0x1 IOCONCLKDIV1 0x2 IOCONCLKDIV2 0x3 IOCONCLKDIV3 0x4 IOCONCLKD...

Page 159: ...ck cycles Input pulses shorter than three filter clocks are rejected 15 13 CLK_DIV Select peripheral clock divider for input filter sampling clock Value 0x7 is reserved 0 0x0 IOCONCLKDIV0 0x1 IOCONCLKDIV1 0x2 IOCONCLKDIV2 0x3 IOCONCLKDIV3 0x4 IOCONCLKDIV4 0x5 IOCONCLKDIV5 0x6 IOCONCLKDIV6 31 16 Reserved Table 206 PIO0_11 register PIO0_11 address 0x4004 401C bit description Bit Symbol Value Descrip...

Page 160: ...x1 IOCONCLKDIV1 0x2 IOCONCLKDIV2 0x3 IOCONCLKDIV3 0x4 IOCONCLKDIV4 0x5 IOCONCLKDIV5 0x6 IOCONCLKDIV6 31 16 Reserved Table 207 PIO0_10 register PIO0_10 address 0x4004 4020 bit description continued Bit Symbol Value Description Reset value Table 208 PIO0_16 register PIO0_16 address 0x4004 4024 bit description Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on c...

Page 161: ... IOCONCLKDIV1 0x2 IOCONCLKDIV2 0x3 IOCONCLKDIV3 0x4 IOCONCLKDIV4 0x5 IOCONCLKDIV5 0x6 IOCONCLKDIV6 31 16 Reserved 0 Table 208 PIO0_16 register PIO0_16 address 0x4004 4024 bit description Bit Symbol Value Description Reset value Table 209 PIO0_15 register PIO0_15 address 0x4004 4028 bit description Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull u...

Page 162: ...NCLKDIV1 0x2 IOCONCLKDIV2 0x3 IOCONCLKDIV3 0x4 IOCONCLKDIV4 0x5 IOCONCLKDIV5 0x6 IOCONCLKDIV6 31 16 Reserved 0 Table 209 PIO0_15 register PIO0_15 address 0x4004 4028 bit description continued Bit Symbol Value Description Reset value Table 210 PIO0_1 register PIO0_1 address 0x4004 402C bit description Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pul...

Page 163: ...NCLKDIV5 0x6 IOCONCLKDIV6 31 16 Reserved 0 Table 210 PIO0_1 register PIO0_1 address 0x4004 402C bit description continued Bit Symbol Value Description Reset value Table 211 PIO0_9 register PIO0_9 address 0x4004 4034 bit description Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor control FAIM value dependent 0x0 Inactive no p...

Page 164: ...on Reset value Table 212 PIO0_8 register PIO0_8 address 0x4004 4038 bit description Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor control FAIM value dependent 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 1 0 Disable 1 Enabl...

Page 165: ...iption Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor control FAIM value dependent 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 1 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin...

Page 166: ...ription Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor control FAIM value dependent 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 1 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pi...

Page 167: ...iption Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor control FAIM value dependent 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 1 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin...

Page 168: ...cription Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor control FAIM value dependent 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 1 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on p...

Page 169: ...scription Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor control FAIM value dependent 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 1 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on ...

Page 170: ...scription Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor control FAIM value dependent 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 1 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on ...

Page 171: ...scription Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor control FAIM value dependent 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 1 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on ...

Page 172: ...scription Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor control FAIM value dependent 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 1 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on ...

Page 173: ...scription Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor control FAIM value dependent 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 1 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on ...

Page 174: ...scription Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor control FAIM value dependent 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 1 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on ...

Page 175: ...scription Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor control FAIM value dependent 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 1 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on ...

Page 176: ...scription Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor control FAIM value dependent 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 1 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on ...

Page 177: ...scription Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor control FAIM value dependent 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 1 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on ...

Page 178: ...scription Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor control FAIM value dependent 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 1 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on ...

Page 179: ...scription Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor control FAIM value dependent 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 1 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on ...

Page 180: ...ription Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor control FAIM value dependent 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 1 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pi...

Page 181: ...n Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor control FAIM value dependent 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 1 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin read...

Page 182: ...ion Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor control FAIM value dependent 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 1 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin re...

Page 183: ...tion Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor control FAIM value dependent 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 1 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin r...

Page 184: ...tion Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor control FAIM value dependent 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 1 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin r...

Page 185: ...on Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor control FAIM value dependent 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 1 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin rea...

Page 186: ...n Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor control FAIM value dependent 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 1 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin read...

Page 187: ...n Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor control FAIM value dependent 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 1 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin read...

Page 188: ...ion Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor control FAIM value dependent 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 1 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin re...

Page 189: ...tion Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor control FAIM value dependent 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 1 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin r...

Page 190: ...on Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor control FAIM value dependent 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 1 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin rea...

Page 191: ...n Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor control FAIM value dependent 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 1 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin read...

Page 192: ...n Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor control FAIM value dependent 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 1 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin read...

Page 193: ...ion Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor control FAIM value dependent 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 1 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin re...

Page 194: ...tion Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor control FAIM value dependent 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 1 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin r...

Page 195: ...on Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor control FAIM value dependent 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 1 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin rea...

Page 196: ...ion Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor control FAIM value dependent 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 1 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin re...

Page 197: ...tion Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor control FAIM value dependent 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 1 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin r...

Page 198: ...on Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor control FAIM value dependent 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 1 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin rea...

Page 199: ...ion Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor control FAIM value dependent 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 1 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin re...

Page 200: ...tion Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor control FAIM value dependent 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 1 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin r...

Page 201: ...tion Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor control FAIM value dependent 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 1 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin r...

Page 202: ...tion Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor control FAIM value dependent 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 1 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin r...

Page 203: ...tion Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor control FAIM value dependent 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 1 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin r...

Page 204: ...tion Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor control FAIM value dependent 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 1 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin r...

Page 205: ...11029 Chapter 11 LPC84x I O configuration IOCON 15 13 CLK_DIV Select peripheral clock divider for input filter sampling clock Value 0x7 is reserved 0 0x0 IOCONCLKDIV0 0x1 IOCONCLKDIV1 0x2 IOCONCLKDIV2 0x3 IOCONCLKDIV3 0x4 IOCONCLKDIV4 0x5 IOCONCLKDIV5 0x6 IOCONCLKDIV6 31 16 Reserved 0 Table 252 PIO1_10 register PIO1_10 address 0x4004 40DC bit description Bit Symbol Value Description Reset value ...

Page 206: ...ys to set pins as inputs or outputs and use the inputs as combinations of level and edge sensitive interrupts The GPIOs can be used as external interrupts together with the pin interrupt block The GPIO port registers configure each GPIO pin as input or output and read the state of each pin if the pin is configured as input or set the state of each pin if the pin is configured as output 12 5 Regist...

Page 207: ...gisters port 0 0 word 32 bit Table 257 DIR1 R W 0x2004 Direction registers port 1 0 word 32 bit Table 257 MASK0 R W 0x2080 Mask register port 0 0 word 32 bit Table 258 MASK1 R W 0x2084 Mask register port 1 0 word 32 bit Table 258 PIN0 R W 0x2100 Port pin register port 0 ext word 32 bit Table 259 PIN1 R W 0x2104 Port pin register port 1 ext word 32 bit Table 259 MPIN0 R W 0x2180 Masked port registe...

Page 208: ...0 PBYTE Read state of the pin PIO0m_n regardless of direction masking or alternate function except that pins configured as analog I O always read as 0 One register for each port pin m port 0 to 1 n pin 0 to 31 for port 0 and pin 0 to 21 for port 1 Write loads the pin s output bit ext R W 7 1 Reserved 0 on read ignored on write 0 Table 256 GPIO port word pin registers W 0 53 addresses 0xA000 1000 W...

Page 209: ...0 2080 MASK0 to 0xA0002084 MASK1 bit description Bit Symbol Description Reset value Access 31 0 MASKP Controls which bits corresponding to PIOm_n are active in the MPORT register bit 0 PIOm_0 bit 1 PIOm_1 bit 31 PIOm_31 m port 0 to 1 n pin 0 to 31 for port 0 and pin 0 to 21 for port 1 0 Read MPORT pin state write MPORT load output bit 1 Read MPORT 0 write MPORT output bit not affected 0 R W Table ...

Page 210: ...ss 0xA000 2200 SET0 to 0xA000 2204 SET1 bit description Bit Symbol Description Reset value Access 31 0 SETP Read or set output bits bit 0 PIOm_0 bit 1 PIOm_1 bit 31 PIOm_31 m port 0 to 1 n pin 0 to 31 for port 0 and pin 0 to 21 for port 1 0 Read output bit write no operation 1 Read output bit write set output bit 0 R W Table 262 GPIO port clear register CLR 0 1 address 0xA000 2280 CLR0 to 0xA000 2...

Page 211: ...m a Byte Pin register The state of a single pin can be read in all bits of a byte halfword or word from a Word Pin register Table 264 GPIO port direction set register DIRSET 0 1 address 0xA000 2380 DIRSET0 to 0xA000 2384 DIRSET1 bit description Bit Symbol Description Reset value Access 31 0 DIRSETP Set direction bits bit 0 PIOm_0 bit 1 PIOm_1 bit 31 PIOm_31 m port 0 to 1 n pin 0 to 31 for port 0 a...

Page 212: ...ges Writing to a port s PORT register loads the output bits of all the pins written to Writing to a port s MPORT register loads the output bits of pins identified by zeros in corresponding positions of the port s MASK register Writing ones to a port s SET register sets output bits Writing ones to a port s CLR register clears output bits Writing ones to a port s NOT register toggles complements inv...

Page 213: ...tput using the DIR registers The direction of individual pins can be set cleared or toggled using the DIRSET DIRCLR and DIRNOT registers 12 6 5 Recommended practices The following lists some recommended uses for using the GPIO port registers For initial setup after Reset or re initialization write the PORT registers To change the state of one pin write a Byte Pin or Word Pin register To change the...

Page 214: ... be programmed to also generate an RXEV notification to the ARM CPU The RXEV signal can be connected to a pin Pattern match can be used in conjunction with software to create complex state machines based on pin inputs 13 3 Basic configuration Pin interrupts Select up to eight external interrupt pins from all GPIO port pins in the SYSCON block Table 167 The pin selection process is the same for pin...

Page 215: ...rk The port pin number serves to identify the pin to the PINTSEL register Any function including GPIO can be assigned to this pin through the switch matrix 3 Enable each pin interrupt in the NVIC Once the pin interrupts or pattern match inputs are configured you can set up the pin interrupt detection levels or the pattern match boolean expression See Section 8 6 42 Pin interrupt select registers i...

Page 216: ...ns to be constructed from the same set of eight GPIO pins that were selected for the GPIO pin interrupts Each term in the boolean expression is implemented as one slice of the pattern match engine A slice consists of an input selector and a detect logic The slice input selector selects one input from the available eight inputs with each input connected to a pin by the input s PINTSEL register The ...

Page 217: ...ct logic block Fig 16 Pattern match engine connections PMSCR bits SCRn n n IN0 IN7 PMSCR bits SCRn 1 IN0 IN7 DETECT LOGIC PINTSEL0 PINTSEL7 NVIC pin interrupt n endpoint configured PMCFG bit n 1 PROD_ENDPTS DETECT LOGIC NVIC pin interrupt n 1 endpoint configured PMCFG bit n 1 1 PROD_ENDPTS tied HIGH for slice 7 from slice n 1 tied HIGH for slice 0 slice n slice n 1 to slice n 2 to IN0 slice n 1 to...

Page 218: ...vel on the selected input Figure 17 shows the details of the edge detection logic for each slice You can combine a sticky event with non sticky events to create a pin interrupt whenever a rising or falling edge occurs after a qualifying edge event You can create a time window during which rising or falling edges can create a pin interrupt by combining a level detect with an event detect See Sectio...

Page 219: ...structed of eight bit slice elements Each bit slice is programmed to represent one component of one minterm product term within the boolean expression The interrupt request associated with the last bit slice for a particular minterm will be asserted whenever that minterm is matched See bit slice drawing Figure 17 The pattern match capability can be used to create complex software state machines Ea...

Page 220: ...er 0 Table 270 SIENR WO 0x008 Pin interrupt level or rising edge interrupt set register NA Table 271 CIENR WO 0x00C Pin interrupt level rising edge interrupt clear register NA Table 272 IENF R W 0x010 Pin interrupt active level or falling edge interrupt enable register 0 Table 273 SIENF WO 0x014 Pin interrupt active level or falling edge interrupt set register NA Table 274 CIENF WO 0x018 Pin inter...

Page 221: ... 0 the rising edge interrupt is set If the pin interrupt mode is level sensitive PMODE 1 the level interrupt is set 13 6 4 Pin interrupt level or rising edge interrupt clear register For each of the 8 pin interrupts selected in the PINTSELn registers see Section 8 6 42 one bit in the CIENR register clears the corresponding bit in the IENR register depending on the pin interrupt mode configured in ...

Page 222: ...ne bit in the SIENF register sets the corresponding bit in the IENF register depending on the pin interrupt mode configured in the ISEL register If the pin interrupt mode is edge sensitive PMODE 0 the falling edge interrupt is set If the pin interrupt mode is level sensitive PMODE 1 the HIGH active interrupt is selected Table 272 Pin interrupt level or rising edge interrupt clear register CIENR ad...

Page 223: ...registers regardless of whether they are interrupt enabled Table 274 Pin interrupt active level or falling edge interrupt set register SIENF address 0xA000 4014 bit description Bit Symbol Description Reset value Access 7 0 SETENAF Ones written to this address set bits in the IENF thus enabling interrupts Bit n sets bit n in the IENF register 0 No operation 1 Select HIGH active interrupt or enable ...

Page 224: ...eneration as opposed to pin interrupts which share the same interrupt request lines and another to enable the RXEV output to the CPU This register also allows the current state of any pattern matches to be read If the pattern match feature is not used either for interrupt generation or for RXEV assertion bits SEL_PMATCH and ENA_RXEV of this register should be left at 0 to conserve power Table 277 ...

Page 225: ... pattern match feature by clearing both the SEL_PMATCH and ENA_RXEV bits in the PMCTRL register to zeros will erase all edge detect history Table 279 Pattern match interrupt control register PMCTRL address 0xA000 4028 bit description Bit Symbol Value Description Reset value 0 SEL_PMATCH Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match func...

Page 226: ...the pin selected in the PINTSEL6 register as the source to bit slice 0 0x7 Input 7 Selects the pin selected in the PINTSEL7 register as the source to bit slice 0 13 11 SRC1 Selects the input source for bit slice 1 0 0x0 Input 0 Selects the pin selected in the PINTSEL0 register as the source to bit slice 1 0x1 Input 1 Selects the pin selected in the PINTSEL1 register as the source to bit slice 1 0x...

Page 227: ...the pin selected in the PINTSEL6 register as the source to bit slice 2 0x7 Input 7 Selects the pin selected in the PINTSEL7 register as the source to bit slice 2 19 17 SRC3 Selects the input source for bit slice 3 0 0x0 Input 0 Selects the pin selected in the PINTSEL0 register as the source to bit slice 3 0x1 Input 1 Selects the pin selected in the PINTSEL1 register as the source to bit slice 3 0x...

Page 228: ...the pin selected in the PINTSEL6 register as the source to bit slice 4 0x7 Input 7 Selects the pin selected in the PINTSEL7 register as the source to bit slice 4 25 23 SRC5 Selects the input source for bit slice 5 0 0x0 Input 0 Selects the pin selected in the PINTSEL0 register as the source to bit slice 5 0x1 Input 1 Selects the pin selected in the PINTSEL1 register as the source to bit slice 5 0x...

Page 229: ...the PINTSEL3 register as the source to bit slice 6 0x4 Input 4 Selects the pin selected in the PINTSEL4 register as the source to bit slice 6 0x5 Input 5 Selects the pin selected in the PINTSEL5 register as the source to bit slice 6 0x6 Input 6 Selects the pin selected in the PINTSEL6 register as the source to bit slice 6 0x7 Input 7 Selects the pin selected in the PINTSEL7 register as the source ...

Page 230: ...t term is detected 2 The next bit slice will start a new independent product term in the boolean expression i e an OR will be inserted in the boolean expression following the element controlled by this bit slice Table 281 Pattern match bit slice configuration register PMCFG address 0xA000 4030 bit description Bit Symbol Value Description Reset value 0 PROD_EN DPTS0 Determines whether slice 0 is an...

Page 231: ...leared This bit is only cleared when the PMCFG or the PMSRC registers are written to 0x2 Sticky falling edge Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared This bit is only cleared when the PMCFG or the PMSRC registers are written to 0x3 Sticky rising or falling edge Match occurs if either a rising or falling...

Page 232: ...her a rising or falling edge is first detected on the specified input this is a non sticky version of value 0x3 This bit is cleared after one clock cycle 16 14 CFG2 Specifies the match contribution condition for bit slice 2 0b000 0x0 Constant HIGH This bit slice always contributes to a product term match 0x1 Sticky rising edge Match occurs if a rising edge on the specified input has occurred since...

Page 233: ...her a rising or falling edge is first detected on the specified input this is a non sticky version of value 0x3 This bit is cleared after one clock cycle 22 20 CFG4 Specifies the match contribution condition for bit slice 4 0b000 0x0 Constant HIGH This bit slice always contributes to a product term match 0x1 Sticky rising edge Match occurs if a rising edge on the specified input has occurred since...

Page 234: ...her a rising or falling edge is first detected on the specified input this is a non sticky version of value 0x3 This bit is cleared after one clock cycle 28 26 CFG6 Specifies the match contribution condition for bit slice 6 0b000 0x0 Constant HIGH This bit slice always contributes to a product term match 0x1 Sticky rising edge Match occurs if a rising edge on the specified input has occurred since...

Page 235: ...put has occurred since the last time the edge detection for this bit slice was cleared This bit is only cleared when the PMCFG or the PMSRC registers are written to 0x3 Sticky rising or falling edge Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared This bit is only cleared when the PMCFG or the ...

Page 236: ... for bit slice 2 SRC3 010 select input 2 for bit slice 3 SRC4 011 select input 3 for bit slice 4 SRC5 110 select input 6 for bit slice 5 SRC6 101 select input 5 for bit slice 6 SRC7 111 select input 7 for bit slice 7 PMCFG register Table 281 PROD_ENDPTS0 1 PROD_ENDPTS02 1 PROD_ENDPTS5 1 All other slices are not product term endpoints and their PROD_ENDPTS bits are 0 Slice 7 is always a product ter...

Page 237: ... match on the last term Bit1 Setting this bit will cause the RxEv signal to the ARM CPU to be asserted whenever a match occurs on ANY of the product terms in the expression Otherwise the RXEV line will not be used Bit31 24 At any given time bits 0 2 5 and or 7 may be high if the corresponding product terms are currently matching The remaining bits will always be low 13 7 3 Pattern match engine edg...

Page 238: ...ction IN1 SRC1 1 CFG1 0x7 PROD_ENPTS1 0x1 non sticky edge detection NVIC pin interrupt 1 and GPIO_INT_BMAT output slice 0 IN0 slice 1 IN1ev minterm IN0 IN1ev pin interrupt raised on rising edge of IN1 during the HIGH level of IN0 Figure shows pattern match functionality only and accurate timing is not implied Inputs INn are shown synchronized to the system clock for simplicity Fig 20 Pattern match...

Page 239: ...nputs to the SCT and DMA triggers Multiplexer inputs from external pins are assigned through the switch matrix to pins 14 5 General description The inputs to the SCTimer PWM and DMA triggers are multiplexed from multiple input sources The sources can be external pins interrupts or output signals of other peripherals The input multiplexing makes it possible to design complex event driven processes ...

Page 240: ...0 SCT0_INMUX3 3 3 0 SCT inputs switch matrix SCT_PIN 0 3 ADC_THCMP_IRQ ACMP_O T0_MAT2 GPIOINT_BMATCH 4 switch matrix SCT_PIN 0 3 ADC_THCMP_IRQ ACMP0_OUT ARM_TXEV DEBUG_HALTED ARM_TXEV DEBUG_HALTED T0_MAT2 GPIOINT_BMATCH 9 8 7 6 5 4 3 0 5 6 7 8 9 Fig 22 DMA trigger multiplexing DMA channel n DMA_INMUX_INMUX0 11 DMA_ITRIG_INMUXn DMA_INMUX_INMUX1 INPUT MUX INP_N INP_N INP_N trigger input from DMA cha...

Page 241: ...rrupts CTIMER32 and DMA requests 0x0F Table 287 DMA_ITRIG_INMUX2 R W 0x048 Input mux register for trigger inputs 0 to 12 connected to DMA channel 2 Selects from ADC SCT ACMP pin interrupts CTIMER32 and DMA requests 0x0F Table 287 DMA_ITRIG_INMUX3 R W 0x04C Input mux register for trigger inputs 0 to 12 connected to DMA channel 3 Selects from ADC SCT ACMP pin interrupts CTIMER32 and DMA requests 0x0...

Page 242: ...s 0 to 12 connected to DMA channel 16 Selects from ADC SCT ACMP pin interrupts CTIMER32 and DMA requests 0x0F Table 287 DMA_ITRIG_INMUX17 R W 0x084 Input mux register for trigger inputs 0 to 12 connected to DMA channel 17 Selects from ADC SCT ACMP pin interrupts CTIMER32 and DMA requests 0x0F Table 287 DMA_ITRIG_INMUX18 R W 0x088 Input mux register for trigger inputs 0 to 12 connected to DMA chann...

Page 243: ...ternal pins through the switch matrix 14 6 3 DMA input trigger input mux registers 0 to 24 With the DMA input trigger input mux registers you can select one trigger input for each of the 25 DMA channels from multiple internal sources By default none of the triggers are selected Table 285 DMA input trigger input mux input registers 0 to 1 DMA_INMUX_INMUX 0 1 address 0x4002 C000 DMA_INMUX_INMUX0 to ...

Page 244: ...ters 0 to 24 DMA_ITRIG_INMUX 0 24 address 0x4002 C040 DMA_ITRIG_INMUX0 to 0x4002 C0A0 DMA_ITRIG_INMUX24 bit description Bit Symbol Value Description Reset value 3 0 INP Trigger input number decimal value for DMA channel n n 0 to 12 All other values are reserved 0x0F 0x0 ADC_SEQA_IRQ 0x1 ADC_SEQB_IRQ 0x2 SCT_DMA0 0x3 SCT_DMA1 0x4 ACMP_O 0x5 PININT4 0x6 PININT5 0x7 PININT6 0x8 PININT7 0x9 T0_DMAREQ_...

Page 245: ...ble 293 If using the WKTCLKIN function disable the hysteresis for that pin in the DPDCTRL register See Table 293 15 3 1 Low power modes in the ARM Cortex M0 core Entering and exiting the low power modes is always controlled by the ARM Cortex M0 core The SCR register is the software interface for controlling the core s actions when entering a low power mode The SCR register is located on the ARM pr...

Page 246: ...trol register SCR address 0xE000 ED10 bit description Bit Symbol Description Reset value 0 Reserved 0 1 SLEEPONEXIT Indicates sleep on exit when returning from Handler mode to Thread mode 0 do not sleep when returning to Thread mode 1 enter sleep or deep sleep on return from an ISR to Thread mode Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main appl...

Page 247: ...ain their internal states The flash memory is powered down The WWDT WKT and BOD can remain active to wake up the system on an interrupt 3 Deep power down mode For maximal power savings the entire system is shut down except for the general purpose registers in the PMU and the self wake up timer Only the general purpose registers in the PMU maintain their internal states The part can wake up on a pu...

Page 248: ...er WDOsc powered in PDSLEEPCFG register WWDT reset WWDT running Enable reset in WWDT MOD register WDOsc powered in PDSLEEPCFG register Self Wake up Timer WKT time out Enable interrupt in NVIC and STARTERP1 registers Enable low power oscillator in the DPDCTRL register in the PCON block Select low power clock for WKT clock in the WKT CTRL register Start the WKT by writing a time out value to the WKT...

Page 249: ... General purpose register 3 0x0 Table 292 DPDCTRL R W 0x014 Deep power down control register Also includes bits for general purpose storage 0x0 Table 293 Table 291 Power control register PCON address 0x4002 0000 bit description Bit Symbol Value Description Reset value 2 0 PM Power mode 000 0x0 Default The part is in active or sleep mode 0x1 Deep sleep mode ARM WFI will enter deep sleep mode 0x2 Po...

Page 250: ...low 2 2 V during deep power down the hysteresis of the WAKEUP or the RESET input pin has to be disabled in this register before entering deep power down mode in order for the chip to wake up Remark Enabling the low power oscillator in deep power down mode increases the power consumption Only enable this oscillator if you need the self wake up timer to wake up the part from deep power down mode You...

Page 251: ... you use the self wake up timer with the low power oscillator clock source to wake up from deep power down mode 0 0 Disabled 1 Enabled 4 WAKEUPCLKHYS External clock input for the self wake up timer WKTCLKIN hysteresis enable 0 0 Disabled Hysteresis for WAKEUP clock pin disabled 1 Enabled Hysteresis for WAKEUP clock pin enabled 5 WAKECLKPAD_ DISABLE Disable the external clock input for the self wak...

Page 252: ...d User manual Rev 1 0 16 June 2017 252 of 515 NXP Semiconductors UM11029 Chapter 15 LPC84x Reduced power modes and power management Remark Do not set bit 1 and bit 7 if you intend to use a pin to wake up the part from deep power down mode You can only disable both wake up pins if the self wake up timer is enabled and configured ...

Page 253: ...ough the PDSLEEPCFG register For details see Section 22 5 3 Using the WWDT lock features 15 7 3 Active mode In Active mode the ARM Cortex M0 core memories and peripherals are clocked by the system clock or main clock The chip is in Active mode after reset and the default power configuration is determined by the reset values of the PDRUNCFG and SYSAHBCLKCTRL registers The power configuration can be...

Page 254: ...heir own clock dividers The peripheral clocks can be shut down through the corresponding clock divider registers 15 7 4 Sleep mode In sleep mode the system clock to the ARM Cortex M0 core is stopped and execution of instructions is suspended until either a reset or an interrupt occurs Peripheral functions if selected to be clocked in the SYSAHBCLKCTRL register continue operation during sleep mode ...

Page 255: ...ontrollers and internal buses The processor state and registers peripheral registers and internal SRAM values are maintained and the logic levels of the pins remain static 15 7 5 1 Power configuration in deep sleep mode Power consumption in deep sleep mode is determined by the deep sleep power configuration setting in the PDSLEEPCFG Table 170 register The watchdog oscillator can be left running in...

Page 256: ... If the BOD is enabled in active mode and the user needs to disable the BOD in deep sleep mode disable the BOD reset bit 4 in the BODCTRL register before entering power down mode After wake up enable the BOD reset bit 4 in the BODCTRL register 15 7 6 Power down mode In power down mode the system clock to the processor is disabled as in sleep mode All analog blocks are powered down except for the B...

Page 257: ...nterrupt must also be enabled in the STARTERP0 register Table 168 and in the NVIC BOD signal if the BOD is enabled in the PDSLEEPCFG register BOD interrupt using the interrupt wake up register 1 Table 169 The BOD interrupt must be enabled in the NVIC The BOD interrupt must be selected in the BODCTRL register Reset from the BOD circuit In this case the BOD reset must be enabled in the BODCTRL regis...

Page 258: ...in the PCON register Table 291 is cleared 3 Write 0x3 to the PM bits in the PCON register see Table 291 4 Store data to be retained in the general purpose registers Section 15 6 2 5 Write one to the SLEEPDEEP bit in the ARM Cortex M0 SCR register Table 288 6 Use the ARM WFI instruction 15 7 7 3 Wake up from deep power down mode using the WAKEUP pin or RESET pin Pulling the WAKEUP pin or RESET pin ...

Page 259: ...T COUNT register Table 425 7 Use the ARM WFI instruction 15 7 7 5 Wake up from deep power down mode using the self wake up timer The part goes through the entire reset process when the self wake up timer times out 1 When the WKT count reaches 0 the following happens The PMU will turn on the on chip voltage regulator When the core voltage reaches the power on reset POR trip point a system reset wil...

Page 260: ...The DMA interrupt is connected to slot 20 in the NVIC Each DMA channel has one DMA request line associated and can also select one of 13 input triggers through the input multiplexer registers DMA_ITRIG_INMUX 0 24 Trigger outputs are connected to DMA_INMUX_INMUX 0 3 as inputs to DMA triggers For details on the trigger input and output multiplexing see Section 14 5 2 DMA trigger input multiplexing 1...

Page 261: ...s Each channel supports one DMA request line and one trigger input which is multiplexed to many possible input sources For each trigger multiplexer DMA_ITRIG_INMUXn the following sources are supported ADC sequence A interrupt ADC_SEQA_IRQ ADC sequence B interrupt ADC_SEQB_IRQ SCT DMA request 0 SCT_DMA0 SCT DMA request 1 SCT_DMA1 ACMP_O comparator output GPIO pin interrupt 4 PININT4 GPIO pin interr...

Page 262: ...p mode 16 4 Pin description The DMA controller has no configurable pins 13 SPI1_TX_DMA DMA_ITRIG_INMUX13 14 I2C0_SLV_DMA DMA_ITRIG_INMUX14 15 I2C0_MST_DMA DMA_ITRIG_INMUX15 16 I2C1_SLV_DMA DMA_ITRIG_INMUX16 17 I2C1_MST_DMA DMA_ITRIG_INMUX17 18 I2C2_SLV_DMA DMA_ITRIG_INMUX18 19 I2C2_MST_DMA DMA_ITRIG_INMUX19 20 I2C3_SLV_DMA DMA_ITRIG_INMUX20 21 I2C3_MST_DMA DMA_ITRIG_INMUX21 22 DAC0_DMAREQ DMA_ITRI...

Page 263: ...s that generate triggers are the SCT the ADC and the analog comparator In addition the DMA triggers also create a trigger output that can trigger DMA transactions on another channel Triggers can be used to send a character or a string to a UART or other serial output at a fixed time interval or when an event occurs A DMA channel using a trigger can respond by moving data from any memory address to...

Page 264: ... 3 The channel descriptor is shown in Table 296 The source and destination end addresses as well as the link to the next descriptor are just memory addresses that can point to any valid address on the device The starting address for both source and destination data is the specified end address minus the transfer length XFERCOUNT the address increment as defined by SRCINC and DSTINC The link to the...

Page 265: ...ons of linked transfers A ping pong transfer uses two buffers alternately At any one time one buffer is being loaded or unloaded by DMA operations The other buffer has the opposite operation being handled by software readying the buffer for use when the buffer currently being used by the DMA controller is full or empty Table 299 shows an example of descriptors for ping pong from a peripheral to tw...

Page 266: ...99 The difference would be that descriptor B would not link back to descriptor A but would continue on to another different descriptor This could continue as long as desired and can be ended anywhere or linked back to any point to repeat a sequence of descriptors Of course any descriptor not currently in use can be altered by software as well 16 5 6 Address alignment for data transfers Transfers o...

Page 267: ...o auto trigger itself setup channels x and y for channel chaining as described above In addition to that A ping pong configuration for both channel x and y is recommended so that data currently moved by channel y is not altered by channel x For channel x Configure the input trigger input mux register DMA_ITRIG_INMUX 0 24 for channel y to use the same DMA trigger mux as chosen for channel y Enable ...

Page 268: ... Transfer configuration register for DMA channel 0 Table 320 Channel1 registers CFG1 R W 0x410 Configuration register for DMA channel 1 Table 317 CTLSTAT1 RO 0x414 Control and status register for DMA channel 1 Table 319 XFERCFG1 R W 0x418 Transfer configuration register for DMA channel 1 Table 320 Channel2 registers CFG2 R W 0x420 Configuration register for DMA channel 2 Table 317 CTLSTAT2 RO 0x42...

Page 269: ...G11 R W 0x4B0 Configuration register for DMA channel 11 Table 317 CTLSTAT11 RO 0x4B4 Control and status register for DMA channel 11 Table 319 XFERCFG11 R W 0x4B8 Transfer configuration register for DMA channel 11 Table 320 Channel12 registers CFG12 R W 0x4C0 Configuration register for DMA channel 12 Table 317 CTLSTAT12 RO 0x4C4 Control and status register for DMA channel 12 Table 319 XFERCFG12 R W...

Page 270: ...egister for DMA channel 20 Table 317 CTLSTAT20 RO 0x544 Control and status register for DMA channel 20 Table 319 XFERCFG20 R W 0x548 Transfer configuration register for DMA channel 20 Table 320 Channel21 registers CFG21 R W 0x550 Configuration register for DMA channel 21 Table 317 CTLSTAT21 RO 0x554 Control and status register for DMA channel 21 Table 319 XFERCFG21 R W 0x558 Transfer configuration...

Page 271: ...e DMA controller is disabled This clears any triggers that were asserted at the point when disabled but does not prevent re triggering when the DMA controller is re enabled 1 Enabled The DMA controller is enabled 31 1 Reserved Read value is undefined only zero should be written NA Table 302 Interrupt Status register INTSTAT address 0x5000 8004 bit description Bit Symbol Value Description Reset val...

Page 272: ...el Writing a 0 to any bit has no effect Enables are cleared by writing to ENABLECLR0 Table 304 Channel descriptor map Descriptor Table offset Channel descriptor for DMA channel 0 0x000 Channel descriptor for DMA channel 1 0x010 Channel descriptor for DMA channel 2 0x020 Channel descriptor for DMA channel 3 0x030 Channel descriptor for DMA channel 4 0x040 Channel descriptor for DMA channel 5 0x050 ...

Page 273: ... register indicates which DMA channels is busy at the point when the read occurs This registers is read only A DMA channel is considered busy when there is any operation related to that channel in the DMA controller s internal pipeline This information can be used after a DMA channel is disabled by software but still active allowing confirmation that there are no remaining operations in progress f...

Page 274: ... position in INTENSET0 that corresponds to an implemented DMA channel sets the bit enabling the interrupt for the related DMA channel Writing a 0 to any bit has no effect Interrupt enables are cleared by writing to INTENCLR0 16 6 10 Interrupt Enable Clear register The INTENCLR0 register is used to clear interrupt enable bits in INTENSET0 The register is write only Table 308 Busy status register 0 ...

Page 275: ...B flag Writing 0 has no effect Any interrupt pending status in this register will be reflected on the DMA interrupt output if it is enabled in the INTENSET register Remark The error status is not included in this register The error status is reported in the ERRINT0 status register 16 6 13 Set Valid register The SETVALID0 register allows setting the Valid bit in the CTRLSTAT register for one or mor...

Page 276: ... bit in the CTRLSTAT register for one or more DMA channel See Section 16 6 17 for a description of the TRIG bit and Section 16 5 1 for a general description of triggering 16 6 15 Abort registers The Abort0 register allows aborting operation of a DMA channel if needed To abort a selected channel the channel should first be disabled by clearing the corresponding Enable bit by writing a 1 to the prop...

Page 277: ...nel 0 0 Active low falling edge Hardware trigger is active low or falling edge triggered based on TRIGTYPE 1 Active high rising edge Hardware trigger is active high or rising edge triggered based on TRIGTYPE 5 TRIGTYPE Trigger Type Selects hardware trigger as edge triggered or level triggered 0 0 Edge Hardware trigger is edge triggered Transfers will be initiated and completed as specified for a s...

Page 278: ...abled the source data address for the DMA is wrapped meaning that the source address range for each burst will be the same As an example this could be used to read several sequential registers from a peripheral for each DMA burst reading the same registers again for each burst 0 0 Disabled Source burst wrapping is not enabled for this DMA channel 1 Enabled Source burst wrapping is enabled for this...

Page 279: ... BURSTPOWER field controls address wrapping if enabled via SrcBurstWrap and or DstBurstWrap and also determines how much data is transferred for each trigger 1 1 0 Hardware DMA trigger is low level sensitive The BURSTPOWER field controls address wrapping if enabled via SrcBurstWrap and or DstBurstWrap and also determines how much data is transferred for each trigger 1 1 1 Hardware DMA trigger is h...

Page 280: ...ked transfers 0 0 Disabled Do not reload the channels control structure when the current descriptor is exhausted 1 Enabled Reload the channels control structure when the current descriptor is exhausted 2 SWTRIG Software Trigger 0 0 When written by software the trigger for this channel is not set A new trigger as defined by the HWTRIGEN TRIGPOL and TRIGTYPE will be needed to start the channel 1 Whe...

Page 281: ...for each transfer 15 14 DSTINC Determines whether the destination address is incremented for each DMA transfer 0 0x0 No increment The destination address is not incremented for each transfer This is the usual case when the destination is a peripheral device 0x1 1 x width The destination address is incremented by the amount specified by Width for each transfer This is the usual case when the destin...

Page 282: ...are Software triggering is accomplished by writing a 1 to the appropriate bit in the SETTRIG register Hardware triggering requires setup of the HWTRIGEN TRIGPOL TRIGTYPE and TRIGBURST fields in the CFG register for the related channel When a channel is initially set up the SWTRIG bit in the XFERCFG register can be set causing the transfer to begin immediately Once triggered transfer on a channel w...

Page 283: ...nd any GPIO as an RTS output Received data and status can optionally be read from a single register Break generation and detection Receive data is 2 of 3 sample voting Status flag set when one sample differs Built in Baud Rate Generator with autobaud function A fractional rate divider is shared among all USARTs Interrupts available for Receiver Ready Transmitter Ready Receiver Idle change in recei...

Page 284: ...YSCON block as follows see Figure 24 1 If a fractional value is needed to obtain a particular baud rate program the fractional divider The fractional divider value is the fraction of MULT DIV The MULT and DIV values are programmed in the FRGCTRL register The DIV value must be programmed with the fixed value of 256 FCLK FRGINPUTCLK 1 MULT DIV The following rules apply for MULT and DIV Always set DI...

Page 285: ... enabled USART interrupt In deep sleep or power down mode you can configure the USART as a wake up source if the USART is configured in synchronous slave mode The USART block can create an interrupt on a received signal even when the USART block receives no clocks from the Fig 24 USART clocking need to draw PDLQBFORFN IUJ FON VHOHFW 5 6 IUR V VBSOO BFON 5 5 9 IUJ FON PDLQBFORFN IUJ FON VHOHFW 5 6 ...

Page 286: ...e mode See Table 323 You must connect the SCLK function to a pin and connect the pin to the master Enable the USART wake up in the STARTERP1 register See Table 169 Start logic 1 interrupt wake up enable register STARTERP1 address 0x4004 8214 bit description Enable the USART interrupt in the NVIC In the PDAWAKE register configure all peripherals that need to be running when the part wakes up The US...

Page 287: ...evice the USART will complete transmitting any character already in progress then stop until CTS is again asserted low U0_SCLK I O external to pin any pin PINASSIGN1 Table 181 Serial clock input output for USART0 n synchronous mode U1_TXD O external to pin any pin PINASSIGN1 Table 181 Transmitter output for USART1 Serial transmit data U1_RXD I external to pin any pin PINASSIGN1 Table 181 Receiver ...

Page 288: ...te Generator block divides the incoming clock to create a 16x baud rate clock in the standard asynchronous operating mode The BRG clock input source is the shared Fractional Rate Generator that runs from the common USART peripheral clock U_PCLK In synchronous slave mode data is transmitted and received using the serial clock directly In synchronous master mode data is transmitted and received usin...

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Page 290: ...NSET R W 0x00C Interrupt Enable read and Set register Contains an individual interrupt enable bit for each potential USART interrupt A complete value may be read from this register Writing a 1 to any implemented bit position causes that bit to be set 0 Table 326 INTENCLR W 0x010 Interrupt Enable Clear register Allows clearing any combination of bits in the INTENSET register Writing a 1 to any impl...

Page 291: ...set again CFG and most other control bits remain unchanged For instance when re enabled the USART will immediately generate a TXRDY interrupt if enabled in the INTENSET register or a DMA transfer request because the transmitter has been reset and is therefore available 1 Enabled The USART is enabled for operation 1 Reserved Read value is undefined only zero should be written NA 3 2 DATALEN Selects...

Page 292: ...XD is sampled on the falling edge of SCLK 1 Rising edge Un_RXD is sampled on the rising edge of SCLK 13 Reserved Read value is undefined only zero should be written NA 14 SYNCMST Synchronous mode Master select 0 0 Slave When synchronous mode is enabled the USART is a slave 1 Master When synchronous mode is enabled the USART is a master 15 LOOP Selects data loopback mode 0 0 Normal operation 1 Loop...

Page 293: ...the standard flow control function 1 Output enable The RTS signal is taken over in order to provide an output enable signal to control an RS 485 transceiver 21 OEPOL Output Enable Polarity 0 0 Low If selected by OESEL the output enable is active low 1 High If selected by OESEL the output enable is active high 22 RXPOL Receive data polarity 0 0 Not changed The RX signal is used as it arrives from t...

Page 294: ...0 Disabled The USART presents all incoming data 1 Enabled The USART receiver ignores incoming data that does not have the most significant bit of the data typically the 9th bit 1 When the data MSB bit 1 the receiver treats the incoming data normally generating a received data interrupt Software can then check the data to see if this is an address that should be handled If it is the ADDRDET bit is ...

Page 295: ... of RX is measured and used the update the BRG register to match the received data rate AUTOBAUD is cleared once this process is complete or if there is an ABERR This bit can be cleared by software when set but only when the UART receiver is idle Disabling the UART in the CFG register also clears the AUTOBAUD bit 31 17 Reserved Read value is undefined only zero should be written NA Table 324 USART...

Page 296: ...ll also be set when this condition occurs because the stop bit s for the character would be missing RXBRK is cleared when the Un_RXD pin goes high 0 RO 11 DELTARXBRK This bit is set when a change in the state of receiver break detection occurs Cleared by software 0 W1 12 START This bit is set when a start is detected on the receiver input Its purpose is primarily to allow wake up from deep sleep o...

Page 297: ...TXDAT register is available to take another character to transmit 0 3 TXIDLEEN When 1 enables an interrupt when the transmitter becomes idle TXIDLE 1 0 4 Reserved Read value is undefined only zero should be written NA 5 DELTACTSEN When 1 enables an interrupt when there is a change in the state of the CTS input 0 6 TXDISEN When 1 enables an interrupt when the transmitter is fully disabled as indica...

Page 298: ...rs the corresponding bit in the INTENSET register 0 3 TXIDLECLR Writing 1 clears the corresponding bit in the INTENSET register 0 4 Reserved Read value is undefined only zero should be written NA 5 DELTACTSCLR Writing 1 clears the corresponding bit in the INTENSET register 0 6 TXDISINTCLR Writing 1 clears the corresponding bit in the INTENSET register 0 7 Reserved Read value is undefined only zero...

Page 299: ...ber of bits that are relevant depends on the USART configuration settings 0 31 9 Reserved the value read from a reserved bit is not defined NA Table 329 USART Receiver Data with Status register RXDATSTAT address 0x4006 4018 USART0 0x4006 8018 USART1 0x4006 C018 USART2 0x4007 0018 USART3 0x4007 4018 USART4 bit description Bit Symbol Description Reset Value 8 0 RXDAT The USART Receiver Data register...

Page 300: ...ving data 2 Disable the USART by writing a 0 to the Enable bit 0 may be written to the entire registers 3 Write the new BRGVAL 4 Write to the CFG register to set the Enable bit to 1 Table 330 USART Transmitter Data Register TXDAT address 0x4006 401C USART0 0x4006 801C USART1 0x4006 C01C USART2 0x4007 001C USART3 0x4007 401C USART4 bit description Bit Symbol Description Reset Value 8 0 TXDAT Writin...

Page 301: ...0 1 Reserved Read value is undefined only zero should be written NA 2 TXRDY Transmitter Ready flag 1 3 TXIDLE Transmitter idle status 1 4 Reserved Read value is undefined only zero should be written NA 5 DELTACTS This bit is set when a change in the state of the CTS input is detected 0 6 TXDISINT Transmitter Disabled Interrupt flag 0 7 Reserved Read value is undefined only zero should be written N...

Page 302: ...g in address detect mode with automatic address matching enabled 17 7 Functional description 17 7 1 Clocking and baud rates In order to use the USART clocking details must be defined such as setting up the BRG and typically also setting up the FRG See Figure 24 Table 333 USART Oversample selection register OSR address 0x4006 4028 USART0 0x4006 4028 USART1 0x4006 8028 USART2 0x4007 0028 USART3 0x40...

Page 303: ... Since the USART normally uses 16x overclocking the jitter in the fractional rate clock in these cases tends to disappear in the ultimate USART output Any of the USARTs on the LPC84x device can use either FRG0 or FRG1 See Table 151 Fractional generator 0 divider value register FRG0DIV address 0x4004 80D0 bit description and Table 152 Fractional generator 0 multiplier value register FRG0MULT addres...

Page 304: ...tware flow control could include XON XOFF flow control or other mechanisms these are supported by the ability to check the current state of the CTS input and or have an interrupt when CTS changes state via the CTS and DELTACTS bits respectively in the STAT register and by the ability of software to gracefully turn off the transmitter via the TXDIS bit in the CTL register 17 7 5 Autobaud function T...

Page 305: ...mpling Typical industry standard UARTs use a 16x oversample clock to transmit and receive asynchronous data This is the number of BRG clocks used for one data bit The Oversample Select Register OSR allows this UART to use a 16x down to a 5x oversample clock There is no oversampling in synchronous modes Reducing the oversampling can sometimes help in getting better baud rate matching when the baud ...

Page 306: ...ng frames of arbitrary length Up to four Slave Select input outputs with selectable polarity and flexible usage Supports DMA transfers SPIn transmit and receive functions can operated with the system DMA controller Remark Texas Instruments SSI and National Microwire modes are not supported 18 3 Basic configuration Configure SPI0 1 using the following registers In the SYSAHBCLKCTRL register set bit...

Page 307: ...r the SPI block is configured in master or slave mode In Deep sleep or Power down mode the SPI clock is turned off as are all peripheral clocks However if the SPI is configured in slave mode and an external master on the provides the clock signal the SPI can create an interrupt asynchronously This interrupt if enabled in the NVIC and in the SPI s INTENSET register can then wake up the core Fig 27 ...

Page 308: ...ion to a pin and connect the pin to the master Enable the SPI interrupt in the STARTERP1 register See Table 169 Start logic 1 interrupt wake up enable register STARTERP1 address 0x4004 8214 bit description In the PDAWAKE register configure all peripherals that need to be running when the part wakes up Enable the SPI interrupt in the NVIC Enable the interrupt in the INTENSET register which configur...

Page 309: ... the master When the SPI is a master serial data is input from this signal When the SPI is a slave serial data is output to this signal MISO is driven when the SPI block is enabled the Master bit in CFG equals 0 and when the slave is selected by one or more SSEL signals SPI0_SSEL0 I O external to pin any pin PINASSIGN4 Table 184 Slave Select 0 When the SPI interface is a master it will drive the S...

Page 310: ...upt enables Fig 28 SPI block diagram MISO MOSI SSEL 3 0 SCK Pad interface Rx Shift Register State Machine Tx Shift Register State Machine SPIn_TXDAT SPIn_RXDAT General controls format configurations 1 SSEL field SPOL RxSSEL SSA SSD SSEL pin levels RxRdy RxOv Clock divider internal clock s DivVal Interrupt control Tx interrupts Rx interrupts SPI interrupt SPI_PCLK Table 336 Register overview SPI ba...

Page 311: ...in INTENSET to be cleared NA Table 341 RXDAT R 0x014 SPI Receive Data NA Table 342 TXDATCTL R W 0x018 SPI Transmit Data with Control 0 Table 343 TXDAT R W 0x01C SPI Transmit Data 0 Table 344 TXCTL R W 0x020 SPI Transmit Control 0 Table 345 DIV R W 0x024 SPI clock Divider 0 Table 346 INTSTAT R 0x028 SPI Interrupt Status 0x02 Table 347 Table 336 Register overview SPI base address 0x4005 8000 SPI0 an...

Page 312: ...e in the SSEL0 fields of the RXDAT TXDATCTL and TXCTL registers related to SSEL0 is not inverted relative to the pins 1 High The SSEL0 pin is active high The value in the SSEL0 fields of the RXDAT TXDATCTL and TXCTL registers related to SSEL0 is inverted relative to the pins 9 SPOL1 SSEL1 Polarity select 0 0 Low The SSEL1 pin is active low The value in the SSEL1 fields of the RXDAT TXDATCTL and TX...

Page 313: ...AY Controls the amount of time between the end of a data transfer and SSEL deassertion 0x0 No additional time is inserted 0x1 1 SPI clock time is inserted 0x2 2 SPI clock times are inserted 0xF 15 SPI clock times are inserted 0 11 8 FRAME_DELAY If the EOF flag is set controls the minimum amount of time between the current frame and the next frame or SSEL deassertion if EOT 0x0 No additional time i...

Page 314: ...XDAT or TXDATCTL until the data is moved to the transmit shift register 1 RO 2 RXOV Receiver Overrun interrupt flag This flag applies only to slave mode Master 0 This flag is set when the beginning of a received character is detected while the receiver buffer is still in use If this occurs the receiver buffer contents are preserved and the incoming data is lost Data received by the SPI should be c...

Page 315: ... process of sending data 1 RO 31 9 Reserved Read value is undefined only zero should be written NA NA Table 339 SPI Status register STAT addresses 0x4005 8008 SPI0 0x4005 C008 SPI1 bit description Bit Symbol Description Reset value Access 1 Table 340 SPI Interrupt Enable read and Set register INTENSET addresses 0x4005 800C SPI0 0x4005 C00C SPI1 bit description Bit Symbol Value Description Reset va...

Page 316: ... Slave Select is deasserted 0 0 No interrupt will be generated when all asserted Slave Selects transition to deasserted 1 An interrupt will be generated when all asserted Slave Selects transition to deasserted 31 6 Reserved Read value is undefined only zero should be written NA Table 340 SPI Interrupt Enable read and Set register INTENSET addresses 0x4005 800C SPI0 0x4005 C00C SPI1 bit description...

Page 317: ...pin for both master and slave operation A zero indicates that a slave select is active The actual polarity of each slave select pin is configured by the related SPOL bit in CFG undefined 18 RXSSEL2_N Slave Select for receive This field allows the state of the SSEL2 pin to be saved along with received data The value will reflect the SSEL2 pin for both master and slave operation A zero indicates tha...

Page 318: ...mply provide two ways to access them For details on the slave select process see Section 18 7 4 For details on using multiple consecutive data transmits for transfer lengths larger than 16 bit see Section 18 7 6 Data lengths greater than 16 bits Table 343 SPI Transmitter Data and Control register TXDATCTL addresses 0x4005 8018 SPI0 0x4005 C018 SPI1 bit description Bit Symbol Value Description Rese...

Page 319: ...e lengths greater than 16 bits 0 0 Data not EOF This piece of data transmitted is not treated as the end of a frame 1 Data EOF This piece of data is treated as the end of a frame causing the FRAME_DELAY time to be inserted before subsequent data is transmitted 22 RXIGNORE Receive Ignore This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver Settin...

Page 320: ...ister determines the clock used by the SPI in master mode For details on clocking see Section 18 7 3 Clocking and data rates Table 344 SPI Transmitter Data Register TXDAT addresses 0x4005 801C SPI0 0x4005 C01C SPI1 bit description Bit Symbol Description Reset value 15 0 DATA Transmit Data This field provides from 4 to 16 bits of data to be transmitted 0 31 16 Reserved Only zero should be written N...

Page 321: ...n Reset Value 15 0 DIVVAL Rate divider value Specifies how the PCLK for the SPI is divided to produce the SPI clock rate in master mode DIVVAL is 1 encoded such that the value 0 results in PCLK 1 the value 1 results in PCLK 2 up to the maximum possible divide value of 0xFFFF which results in PCLK 65536 0 31 16 Reserved Read value is undefined only zero should be written NA Table 347 SPI Interrupt ...

Page 322: ...CPOL CPHA SPI Mode Description SCKrest state SCK data change edge SCK data sample edge 0 0 0 The SPI captures serial data on the first clock transition of the transfer when the clock changes away from the rest state Data is changed on the following edge low falling rising 0 1 1 The SPI changes serial data on the first clock transition of the transfer when the clock changes away from the rest state...

Page 323: ... minimum duration of SSEL in the de asserted state between transfers 18 7 2 1 Pre_delay and Post_delay Pre_delay and Post_delay are illustrated by the examples in Figure 30 The Pre_delay value controls the amount of time between SSEL being asserted and the beginning of the subsequent data frame The Post_delay value controls the amount of time between the end of a data frame and the de assertion of...

Page 324: ...y the examples in Figure 31 Note that frame boundaries occur only where specified This is because frame lengths can be any size involving multiple data writes See Section 18 7 6 for more information Fig 31 Frame_delay Frame delay CPHA 0 Frame_delay 2 Pre_delay 0 Post_delay 0 Mode 2 CPOL 1 SCK Frame_delay Mode 0 CPOL 0 SCK MSB LSB MSB LSB MISO MOSI SSEL MSB MSB Second data frame LSB LSB Frame delay...

Page 325: ...ransfers because the EOT bit 1 When Transfer_delay 0 SSEL may be de asserted for a minimum of one SPI clock time Transfer_delay is illustrated by the examples in Figure 32 Fig 32 Transfer_delay Transfer delay Transfer_delay 1 Pre_delay 0 Post_delay 0 SCK CPOL 1 Transfer _delay SCK CPOL 0 MSB LSB MSB LSB MISO MOSI SSEL Transfer delay Transfer_delay 1 Pre_delay 0 Post_delay 0 MSB LSB MSB LSB MISO MO...

Page 326: ...s the selected PCLK or at lower integer divide rates The SPI rate will be PCLK_SPIn DIVVAL In slave mode the clock is taken from the SCK input and the SPI clock divider is not used 18 7 4 Slave select The SPI block provides for four Slave Select inputs in slave mode or outputs in master mode Each SSEL can be set for normal polarity active low or can be inverted active high Representation of the 4 ...

Page 327: ...er data widths depend somewhat on other SPI configuration options For instance if it is intended for Slave Selects to be de asserted between frames then this must be suppressed when a larger frame is split into more than one part Sending 2 groups of 12 bits with SSEL de asserted between 24 bit increments for instance would require changing the value of the EOF bit on alternate 12 bit frames 18 7 7...

Page 328: ...t_delay 0 2 clock stall Mode 2 CPOL 1 SCK Mode 0 CPOL 0 SCK MISO MOSI Second data frame Receiver stall CPHA 1 Frame_delay 0 Pre_delay 0 Post_delay 0 2 clock stall MISO MOSI Mode 1 CPOL 0 SCK Mode 3 CPOL 1 SCK Second data frame First data frame First data frame Receiver stall CPHA 0 Frame_delay 0 Pre_delay 0 Post_delay 0 2 clock stall Mode 2 CPOL 1 SCK Mode 0 CPOL 0 SCK MISO MOSI Second data frame ...

Page 329: ...be selectively qualified with a bit mask or an address range in order to respond to multiple I2C bus addresses 10 bit addressing supported with software assist Supports System Management SMBus Separate DMA requests for Master and Slave Supports the I2C bus specification up to Fast mode Plus up to 1 MHz 19 3 Basic configuration Configure the I2C interfaces using the following registers In the SYSAH...

Page 330: ...e other I2C blocks to pins through the switch matrix See Table 349 For a 400 kHz bit rate the I2C0 pins can be configured in standard mode in the IOCON block See Table 206 PIO0_11 register PIO0_11 address 0x4004 401C bit description and Table 207 PIO0_10 register PIO0_10 address 0x4004 4020 bit description Gray shaded blocks show peripherals that can provide hardware triggers or fixed DMA requests...

Page 331: ...read or write to the MSTDAT register and go to the next step of the transmission protocol by writing to the MSTCTL register Configure the I2C bit rate Divide the system clock I2C_PCLK by a factor of 2 See Table 358 I2C Clock Divider register CLKDIV address 0x4005 0014 I2C0 0x4005 4014 I2C1 0x4003 0014 I2C2 0x4003 4014 I2C3 bit description Set the SCL high and low times to 2 clock cycles each This ...

Page 332: ...s 6 Wait for the pending status to be set MSTPENDING 1 by polling the STAT register 7 Stop the transmission by setting the MSTSTOP bit to 1 in the Master control register See Table 360 19 3 1 2 Master read from slave Configure the I2C as master Set the MSTEN bit to 1 in the CFG register See Table 351 Read data from the slave 1 Write the slave address with the RW bit set to 1 to the Master data reg...

Page 333: ...d data The received data or the data to be sent to the master are available in the SLVDAT register After sending and receiving data continue to the next step of the transmission protocol by writing to the SLVCTL register 19 3 2 1 Slave read from master Configure the I2C as slave with address x Set the SLVEN bit to 1 in the CFG register See Table 351 Write the slave address x to the address 0 match...

Page 334: ...as the I2C clock I2C_PCLK remains active in sleep mode the I2C can wake up the part independently of whether the I2C block is configured in master or slave mode In Deep sleep or Power down mode the I2C clock is turned off as are all peripheral clocks However if the I2C is configured in slave mode and an external master on the I2C bus provides the clock signal the I2C block can create an interrupt ...

Page 335: ... PIO0_10 register PIO0_10 address 0x4004 4020 bit description Pins for the I2C1 2 3 interfaces are movable functions and can be assigned to any pin However except for PIO0_10 and PIO0_11 the pins are not open drain and do not support Fast mode Plus mode Bit rates of 400 kHz are supported on all pins 19 5 General description The architecture of the I2C bus interface is shown in Figure 35 Table 349 ...

Page 336: ...iconductors N V 2017 All rights reserved User manual Rev 1 0 16 June 2017 336 of 515 NXP Semiconductors UM11029 Chapter 19 LPC84x I2C0 1 2 3 Fig 35 I2C block diagram Time out I 2 C master function I 2 C slave function I2Cn_SDA I2Cn_SCL SCL SDA output logic Timing generation Monitor function ...

Page 337: ...nctions 0 Table 359 MSTCTL R W 0x20 Master control register 0 Table 360 MSTTIME R W 0x24 Master timing configuration 0x77 Table 361 MSTDAT R W 0x28 Combined Master receiver and transmitter data register NA Table 362 SLVCTL R W 0x40 Slave control register 0 Table 363 SLVDAT R W 0x44 Combined Slave receiver and transmitter data register NA Table 364 SLVADR0 R W 0x48 Slave address 0 0x01 Table 365 SL...

Page 338: ...abled Both types of time out flags will be generated and will cause interrupts if they are enabled Typically only one time out will be used in a system 4 MONCLKSTR Monitor function Clock Stretching 0 0 Disabled The monitor function will not perform clock stretching Software or DMA may not always be able to read data provided by the monitor function before it is overwritten This mode may be used wh...

Page 339: ...In progress Communication is in progress and the Master function is busy and cannot currently accept a command 1 Pending The Master function needs software service or is in the idle state If the master is not in the idle state it is waiting to receive or transmit data or the NACK bit 3 1 MSTSTATE Master State code The master state code reflects the master state when the MSTPENDING bit is set that ...

Page 340: ... only and is automatically cleared when a 1 is written to the SLVCONTINUE bit in the MSTCTL register 0 RO 0 In progress The Slave function does not currently need service 1 Pending The Slave function needs service Information on what is needed can be found in the adjacent SLVSTATE field 10 9 SLVSTATE Slave State code Each value of this field indicates a specific required service for the Slave func...

Page 341: ... will cause an interrupt when set if enabled via INTENSET This flag can be cleared by writing a 1 to this bit 0 W1 0 Not deselected The Slave function has not become deselected This does not mean that it is currently selected That information can be found in the SLVSEL flag 1 Deselected The Slave function has become deselected This is specifically caused by the SLVSEL flag changing from 1 to 0 See...

Page 342: ...t The time between I2C bus events has been longer than the time specified by the I2C TIMEOUT register 25 SCLTIMEOUT SCL Time out Interrupt flag Indicates when SCL has remained low longer than the time specific by the TIMEOUT register The flag is cleared by writing a 1 to this bit 0 W1 0 No time out SCL low time has not caused a time out 1 Time out SCL low time has caused a time out 31 26 Reserved ...

Page 343: ...3 regarding 10 bit addressing No 1 SLVST_RX Received data is available Slave Receiver mode Read data reply with an ACK or a NACK Yes 2 SLVST_TX Data can be transmitted Slave Transmitter mode Send data Yes 3 Reserved Table 355 Interrupt Enable Set and read register INTENSET address 0x4005 0008 I2C0 0x4005 4008 I2C1 0x4003 0008 I2C2 0x4003 4008 I2C3 bit description Bit Symbol Value Description Reset...

Page 344: ...eSel interrupt is enabled 16 MONRDYEN Monitor data Ready interrupt Enable 0 0 The MonRdy interrupt is disabled 1 The MonRdy interrupt is enabled 17 MONOVEN Monitor Overrun interrupt Enable 0 0 The MonOv interrupt is disabled 1 The MonOv interrupt is enabled 18 Reserved Read value is undefined only zero should be written NA 19 MONIDLEEN Monitor Idle interrupt Enable 0 0 The MonIdle interrupt is dis...

Page 345: ...ymbol Description Reset value 0 MSTPENDINGCLR Master Pending interrupt clear Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented 0 3 1 Reserved Read value is undefined only zero should be written NA 4 MSTARBLOSSCLR Master Arbitration Loss interrupt clear 0 5 Reserved Read value is undefined only zero should be written NA 6 MSTSTSTPERRCLR Master Start Stop Err...

Page 346: ...10 I2C1 0x4003 0010 I2C2 0x4003 4010 I2C3 bit description Bit Symbol Description Reset value 3 0 TOMIN Time out time value bottom four bits These are hard wired to 0xF This gives a minimum time out of 16 I2C function clocks and also a time out resolution of 16 I2C function clocks 0xF 15 4 TO Time out time value Specifies the time out interval value in increments of 16 I2C function clocks as define...

Page 347: ...ew data following a Start or Stop may cause undesirable side effects Table 359 I2C Interrupt Status register INTSTAT address 0x4005 0018 I2C0 0x4005 4018 I2C1 0x4003 0018 I2C2 0x4003 4018 I2C3 bit description Bit Symbol Description Reset value 0 MSTPENDING Master Pending 1 3 1 Reserved 4 MSTARBLOSS Master Arbitration Loss flag 0 5 Reserved Read value is undefined only zero should be written NA 6 M...

Page 348: ...ymbol Value Description Reset value 0 MSTCONTINUE Master Continue This bit is write only 0 0 No effect 1 Continue Informs the Master function to continue to the next operation This must done after writing transmit data reading received data or any other housekeeping related to the next bus operation 1 MSTSTART Master Start control This bit is write only 0 0 No effect 1 Start A Start will be genera...

Page 349: ... lengthen this time This corresponds to the parameter tLOW in the I2C bus specification I2C bus specification parameters tBUF and tSU STA have the same values and are also controlled by MSTSCLLOW 0x7 0x0 2 clocks Minimum SCL low time is 2 clocks of the I2C clock pre divider 0x1 3 clocks Minimum SCL low time is 3 clocks of the I2C clock pre divider 0x2 4 clocks Minimum SCL low time is 4 clocks of t...

Page 350: ...lock pre divider 0x2 4 clocks Minimum SCL high time is 4 clock of the I2C clock pre divider 0x3 5 clocks Minimum SCL high time is 5 clock of the I2C clock pre divider 0x4 6 clocks Minimum SCL high time is 6 clock of the I2C clock pre divider 0x5 7 clocks Minimum SCL high time is 7 clock of the I2C clock pre divider 0x6 8 clocks Minimum SCL high time is 8 clock of the I2C clock pre divider 0x7 9 cl...

Page 351: ...t Symbol Value Description Reset Value 0 SLVCONTINUE Slave Continue 0 0 No effect 1 Continue Informs the Slave function to continue to the next operation This must done after writing transmit data reading received data or any other housekeeping related to the next bus operation 1 SLVNACK Slave NACK 0 0 No effect 1 NACK Causes the Slave function to NACK the master when the slave is receiving data f...

Page 352: ...rs do not include the address qualifier feature For handling of the general call address one of the 4 address registers can be programmed to respond to address 0 19 6 14 Slave address Qualifier 0 register The SLVQUAL0 register can alter how Slave Address 0 is interpreted Table 365 Slave Address registers SLVADR 0 3 address 0x4005 0048 SLVADR0 to 0x4005 0054 SLVADR3 I2C0 0x4005 4048 SLVADR0 to 0x40...

Page 353: ...tion from the I2C bus Table 366 Slave address Qualifier 0 register SLVQUAL0 address 0x4005 0058 I2C0 0x4005 4058 I2C1 0x4003 0058 I2C2 0x4003 4058 I2C3 bit description Bit Symbol Value Description Reset Value 0 QUALMODE0 Reserved Read value is undefined only zero should be written 0 0 The SLVQUAL0 field is used as a logical mask for matching address 0 1 The SLVQUAL0 field is used to extend address...

Page 354: ...IV 1 MSTSCLLOW 2 Nominal SCL rate I2C function clock rate SCL high time SCL low time Remark DIVVAL must be 1 Remark For 400 KHz clock rate the clock frequency after the I2C divider divval must be 2 MHz Table 368 shows the recommended settings for 400 KHz clock rate 8 MONSTART Monitor Received Start 0 0 No detect The monitor function has not detected a Start event on the I2C bus 1 Start detect The ...

Page 355: ...bus will be released unless it is a current master causing the problem Refer to the SMBus specification for more details Both types of time out are generated when the I2C bus is considered busy 19 7 3 Ten bit addressing Ten bit addressing is accomplished by the I2C master sending a second address byte to extend a particular range of standard 7 bit addresses In the case of the master writing to the...

Page 356: ... and power considerations The Master function of the I2C always requires a peripheral clock to be running in order to operate The Slave function can operate without any internal clocking when the slave is not currently addressed This means that reduced power modes up to Power down mode can be entered and the device will wake up when the I2C Slave function recognizes an address Monitor mode can sim...

Page 357: ...ptional interrupt generation on match Optional auto reload from match shadow registers when counter is reset Stop timer on match with optional interrupt generation Reset timer on match with optional interrupt generation Up to 4 external outputs corresponding to match registers with the following capabilities the number of match outputs that are actually available on device pins may vary by device ...

Page 358: ...registers can be used to provide a single edge controlled PWM output on the match output pins One match register is used to control the PWM cycle length All match registers can optionally be auto reloaded from a companion shadow register whenever the counter is reset to zero This permits modifying the match values for the next counter cycle without risk of disrupting the PWM waveforms during the c...

Page 359: ...2 bit counter timer block diagram RQWURO 0DWFK 5HJLVWHUV 05 WR 05 RPSDUH 0DWFK RQWURO UHJLVWHU 0 5 7LPHU RXQWHU 7 DSWXUH 5HJLVWHUV 5 WR 5 3UHVFDOH RXQWHU 3 3UHVFDOH 5HJLVWHU 35 7LPHU RQWURO 5HJLVWHU 7 5 0DWFK 6KDGRZ 5HJLVWHUV 065 WR 065 5HVHW RQ PDWFK 0 7 0 UHTXHVW 6WRS RQ PDWFK 3 QWHUUXSW 2 WLPHU IXQFWLRQ FORFN QDEOH 5HVHW QDEOH 5HVHW RXQW HQDEOH DSWXUH RQWURO 5HJLVWHU 5 WHUQDO 0DWFK 5HJLVWHU 05 ...

Page 360: ...ured to load one of the Capture Registers with the value in the Timer Counter and optionally generate an interrupt Capture functionality can be selected from a number of pins Timer Counter block can select a capture signal as a clock source instead of the APB bus clock For more details see Section 20 7 11 CTIMER0_MAT2 0 Output Any pin PINASSIGN13 External Match Output When a match register equals ...

Page 361: ... whether an interrupt is generated whether the TC is reset when a Match occurs and whether the match register is reloaded from its shadow register when the TC is reset 0 20 7 6 MR0 R W 0x18 Match Register 0 MR0 can be enabled through the MCR to reset the TC stop both the TC and PC and or generate an interrupt every time MR0 matches the TC 0 20 7 7 MR1 R W 0x1C Match Register 1 See MR0 description ...

Page 362: ...tch 1 Register will be automatically reloaded with the contents of this register whenever the TC is reset to zero 0 20 7 13 MSR2 R W 0x80 Match 2 Shadow Register If enabled the Match 2 Register will be automatically reloaded with the contents of this register whenever the TC is reset to zero 0 20 7 13 MSR3 R W 0x84 Match 3 Shadow Register If enabled the Match 3 Register will be automatically reloa...

Page 363: ... This event does not cause an interrupt but a match register can be used to detect an overflow if needed Table 371 Interrupt Register IR offset 0x00 bit description Bit Symbol Description Reset Value 0 MR0INT Interrupt flag for match channel 0 0 1 MR1INT Interrupt flag for match channel 1 0 2 MR2INT Interrupt flag for match channel 2 0 3 MR3INT Interrupt flag for match channel 3 0 4 CR0INT Interru...

Page 364: ...31 0 PRVAL Prescale counter value 0 Table 375 Timer prescale counter register PC offset 0x10 bit description Bit Symbol Description Reset value 31 0 PCVAL Prescale counter value 0 Table 376 Match Control Register MCR offset 0x14 bit description Bit Symbol Description Reset Value 0 MR0I Interrupt on MR0 an interrupt is generated when MR0 matches the value in the TC 0 disabled 1 enabled 0 1 MR0R Res...

Page 365: ...nd falling bits at the same time is a valid configuration resulting in a capture event for both edges In the description below n represents the timer number 0 or 1 Note If Counter mode is selected for a particular CAP input in the CTCR the 3 bits for that input in this register should be programmed as 000 but capture and or interrupt can be selected for the other 3 CAP inputs 11 MR3S Stop on MR3 t...

Page 366: ...quence of 0 then 1 causes CR0 to be loaded with the contents of TC 0 disabled 1 enabled 0 1 CAP0FE Falling edge of capture channel 0 a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC 0 disabled 1 enabled 0 2 CAP0I Generate interrupt on channel 0 capture event a CR0 load generates an interrupt 0 3 CAP1RE Rising edge of capture channel 1 a sequence of 0 then 1 causes CR1 to be l...

Page 367: ...atch occurs between the TC and MR3 this bit can either toggle go LOW go HIGH or do nothing as selected by MR 11 10 This bit is driven to the MAT pins if the match function is selected via IOCON 0 LOW 1 HIGH 0 5 4 EMC0 External Match Control 0 Determines the functionality of External Match 0 0 0x0 Do Nothing 0x1 Clear Clear the corresponding External Match bit output to 0 MAT0 pin is LOW if pinned ...

Page 368: ...llows for a designated edge on a particular CAP input to reset the timer to all zeros Using this mechanism to clear the timer on the leading edge of an input pulse and performing a capture on the trailing edge permits direct pulse width measurement using a single capture input without the need to perform a subtraction operation in software Table 381 Count Control Register CTCR offset 0x70 bit desc...

Page 369: ...e of the signal on capture channel 0 clears the timer if bit 4 is set 0x1 Channel 0 Falling Edge Falling edge of the signal on capture channel 0 clears the timer if bit 4 is set 0x2 Channel 1 Rising Edge Rising edge of the signal on capture channel 1 clears the timer if bit 4 is set 0x3 Channel 1 Falling Edge Falling edge of the signal on capture channel 1 clears the timer if bit 4 is set 0x4 Chan...

Page 370: ... also be programmed to generate an interrupt or DMA request Software or the DMA engine will then have one full counter cycle to modify the contents of the Match Shadow Register s before the next reload occurs 3 PWMEN3 PWM mode enable for channel3 Note It is recommended to use match channel 3 to set the PWM cycle 0 0 Match CTIMER_MAT3 is controlled by EM3 1 PWM PWM mode is enabled for CTIMER_MAT3 3...

Page 371: ... clock after the timer reaches the match value the timer enable bit in TCR is cleared and the interrupt indicating that a match occurred is generated 20 8 1 Rules for single edge controlled PWM outputs 1 All single edge controlled PWM outputs go LOW at the beginning of each PWM cycle timer is set to zero unless their match value is equal to zero 2 Each PWM output will go HIGH when its match value ...

Page 372: ...peration DMA requests are generated by a match of the Timer Counter TC register value to either Match Register 0 MR0 or Match Register 1 MR1 This is not connected to the operation of the Match outputs controlled by the EMR register Each match sets a DMA request flag which is connected to the DMA controller In order to have an effect the DMA controller must be configured correctly When a timer is i...

Page 373: ...ansition or level create events to accomplish any or all of the following stop limit or halt the timer change counting direction set clear or toggle outputs change the state capture the counter value generate an interrupt or DMA request Counter value can be loaded into capture register triggered by a match or input output toggle PWM features Counters can be used in conjunction with match registers...

Page 374: ...events can occur in that state A state changes into some other state as a result of an event Each event can be assigned to one or more states State variable allows sequencing across multiple counter cycles 21 3 Basic configuration Configure the SCTimer PWM as follows Enable the clock to the SCTimer PWM in the SYSAHBCLKCTRL register Section 8 6 21 to enable the register interface and the peripheral...

Page 375: ...SCT inputs SCT_PIN 0 3 SCT_OUT 0 6 ADC_THCMP_IRQ ACMP0 output ARM_TXEV DEBUG_HALTED 4 4 6 ADC_THCMP_IRQ ACMP0 output ARM_TXEV DEBUG_HALTED SWITCH MATRIX PINASSIGN 6 9 ADC trigger Table 384 SCTimer PWM pin description Function Type Connect to Use register Reference Description SCT input 0 SCT input 1 SCT input 2 SCT input 3 SCT input 4 external to pins or internal one of the following SCT_PIN 0 3 t...

Page 376: ...the count value into any capture registers Generate an interrupt or DMA request The SCTimer PWM allows the user to group and filter events thereby selecting some events to be enabled together while others are disabled A group of enabled and disabled events can be described as a state and several states with different sets of enabled and disabled events are allowed Changing from one state to anothe...

Page 377: ... other on chip resources comparators ADC triggers other timers etc in addition to general purpose I O In addition to events and states the SCTimer PWM provides other enhanced features Four alternative clocking modes including a fully asynchronous mode Selection of any SCTimer PWM input as a clock source or a clock gate Capability of selecting a greater than or equal to match condition for the purp...

Page 378: ... L and H registers by a 32 bit read or write operation or can be read or written to individually for operation as two 16 bit counter timers Typically the UNIFY bit is configured by writing to the CONFIG register before any other registers are accessed 2 The REGMODEn bits in the REGMODE register determine whether each set of Match Capture registers uses the match or capture functionality REGMODEn 0...

Page 379: ...4 SCT state register 0x0000 0000 21 6 9 STATE_L R W 0x044 SCT state register low counter 16 bit 0x0000 0000 21 6 9 STATE_H R W 0x046 SCT state register high counter 16 bit 0x0000 0000 21 6 9 INPUT RO 0x048 SCT input register 0x0000 0000 21 6 10 REGMODE R W 0x04C SCT match capture mode register 0x0000 0000 21 6 11 REGMODE_L R W 0x04C SCT match capture mode register low counter 16 bit 0x0000 0000 21...

Page 380: ... REGMODE0 1 to REGMODE7 1 0x0000 0000 21 6 23 EV0_STATE R W 0x300 SCT event state register 0 0x0000 0000 21 6 24 EV0_CTRL R W 0x304 SCT event control register 0 0x0000 0000 21 6 25 EV1_STATE R W 0x308 SCT event state register 1 0x0000 0000 21 6 24 EV1_CTRL R W 0x30C SCT event control register 1 0x0000 0000 21 6 25 EV2_STATE R W 0x310 SCT event state register 2 0x0000 0000 21 6 24 EV2_CTRL R W 0x31...

Page 381: ...r each event OUT3_SET R W 0x518 SCT output 3 set register 0x0000 0000 21 6 26 OUT3_CLR R W 0x51C SCT output 3 clear register 0x0000 0000 21 6 27 OUT4_SET R W 0x520 SCT output 4 set register 0x0000 0000 21 6 26 OUT4_CLR R W 0x524 SCT output 4 clear register 0x0000 0000 21 6 27 OUT5_SET R W 0x528 SCT output 5 set register 0x0000 0000 21 6 26 OUT5_CLR R W 0x52C SCT output 5 clear register 0x0000 0000...

Page 382: ...OUT 5 0 _CLR SET CLRm yes no select event m to capture the counter value in CAPn CAPCTRL 7 0 CAPCTRL CAPCONm yes no select event m to limit the counter LIMIT LIMMSKm event m event m event m event m yes no select event m to raise the SCT interrupt EVEN IENm event m yes no select event m to trigger DMA requests 0 and 1 DMAREQ0 1 DEV_0 1m event m outputs 6 0 yes no event m CAP 7 0 select event m to h...

Page 383: ...s associated with a match reload register which automatically reloads the match register at the beginning of each counter cycle This register group includes the following registers One REGMODE register per match capture register to configure each match capture register for either storing a match value or a capture value A set of match capture registers with each register depending on the setting o...

Page 384: ...events can be selected independently for each output 21 6 1 6 Event select registers for capturing a counter value This group contains registers that select events which capture the counter value and store it in one of the CAP registers Each capture register m has one associated CAPCTRLm register which in turn selects the events to capture the counter value 21 6 1 7 Event select register for initi...

Page 385: ...input edge selected by the CKSEL field clocks the SCTimer PWM module including the counters and prescalers after first being synchronized to the system clock The minimum width of the positive and negative phases of the clock input must each be greater than one full period of the bus system clock 0x3 Asynchronous Mode The entire SCTimer PWM module is clocked directly by the input edge selected by t...

Page 386: ...imer PWM clock The SCTimer PWM clock frequency does not exceed 100 MHz Note The SCTimer PWM clock is the bus system clock for CKMODE 0 2 or the selected asynchronous input clock for CKMODE3 Alternatively for CKMODE2 only it is also allowable to bypass synchronization if both of the following conditions are met The corresponding input is synchronous to the designated CKMODE2 input clock The CKMODE2...

Page 387: ...events related to the counter can occur If a designated start event occurs this bit is cleared and counting resumes 0 2 HALT_L When this bit is 1 the L or unified counter does not run and no events can occur A reset sets this bit When the HALT_L bit is one the STOP_L bit is cleared It is possible to remove the halt condition while keeping the SCTimer PWM in the stop condition not running with a si...

Page 388: ...le disable this feature see Table 386 If UNIFY 1 in the CONFIG register only the _L bits are used If UNIFY 0 in the CONFIG register this register can be written to as two registers LIMIT_L and LIMIT_H Both the L and H registers can be read or written individually or in a single 32 bit read or write operation 18 HALT_H When this bit is 1 the H counter does not run and no events can occur A reset se...

Page 389: ...n a single 32 bit read or write operation 21 6 6 SCTimer PWM stop event select register The running counter can be stopped by an event When any of the events selected in this register occur counting is suspended that is the counter stops running and remains at its current value Event generation remains enabled and any event selected in the START register such as an I O event or an event generated ...

Page 390: ...erve as a START event When any START event occurs hardware will clear the STOP bit in the Control Register CTRL Note that a START event has no effect on the HALT bit Only software can remove a HALT condition To define the actual event that starts the counter an I O pin toggle or an event generated by the other running counter in dual counter mode see the EVn_CTRL register If UNIFY 1 in the CONFIG ...

Page 391: ...ents 0 2 and 3 enabled and all other events disabled A state variable with the value of 1 could have events 1 4 and 5 enabled and all others disabled Remark The EVm_STATE registers define which event is enabled in each group Software can read the state associated with a counter at any time Writing to the STATE_L STATE_H or unified register is only allowed when the corresponding counter is halted H...

Page 392: ...egister in slightly different forms 1 The AIN bit displays the state of the input captured on each rising edge of the SCTimer PWM clock This corresponds to a nearly direct read out of the input but can cause spurious fluctuations in case of an asynchronous input signal 2 The SIN bit displays the form of the input as it is used for event detection This may include additional stages of synchronizati...

Page 393: ...h register Section 21 6 22 or as a Capture Control register event select when the register is used as a capture register Section 21 6 23 REGMODE_H is used only when the UNIFY bit is 0 16 SIN0 Input 0 state Input 0 state following the synchronization specified by INSYNC0 17 SIN1 Input 1 state Input 1 state following the synchronization specified by INSYNC1 18 SIN2 Input 2 state Input 2 state follow...

Page 394: ...offset 0x050 bit description Bit Symbol Description Reset value 6 0 OUT Writing a 1 to bit n forces the corresponding output HIGH Writing a 0 forces the corresponding output LOW output 0 bit 0 output 1 bit 1 output 6 bit 6 0 31 6 Reserved Table 397 SCTimer PWM bidirectional output control register OUTPUTDIRCTRL offset 0x054 bit description Bit Symbol Value Description Reset value 1 0 SETCLR0 Set c...

Page 395: ...nd on the direction of any counter 0x1 Set and clear are reversed when counter L or the unified counter is counting down 0x2 Set and clear are reversed when counter H is counting down Do not use if UNIFY 1 13 12 SETCLR6 Set clear operation on output 6 0 0x0 Set and clear do not depend on the direction of any counter 0x1 Set and clear are reversed when counter L or the unified counter is counting d...

Page 396: ...lear output n or set based on the SETCLR2 field 0x3 Toggle output 7 6 O3RES Effect of simultaneous set and clear on output 3 0 0x0 No change 0x1 Set output or clear based on the SETCLR3 field in the OUTPUTDIRCTRL register 0x2 Clear output or set based on the SETCLR3 field 0x3 Toggle output 9 8 O4RES Effect of simultaneous set and clear on output 4 0 0x0 No change 0x1 Set output or clear based on t...

Page 397: ...only bit indicates the state of DMA Request 0 Note that if the related DMA channel is enabled and properly set up it is unlikely that software will see this flag it will be cleared rapidly by the DMA service The flag remaining set could point to an issue with DMA setup 0 Table 400 SCTimer PWM DMA 1 request register DMAREQ1 offset 0x060 bit description Bit Symbol Description Reset value 5 0 DEV_1 I...

Page 398: ...re both 0 Table 402 SCTimer PWM event flag register EVFLAG offset 0x0F4 bit description Bit Symbol Description Reset value 7 0 FLAG Bit n is one if event n has occurred since reset or a 1 was last written to this bit event 0 bit 0 event 1 bit 1 event 7 bit 7 0 31 8 Reserved Table 403 SCTimer PWM conflict interrupt enable register CONEN offset 0x0F8 bit description Bit Symbol Description Reset valu...

Page 399: ...GMODEn bit 0 A Match register L H or unified 32 bit is loaded from its corresponding Reload register at the start of each new counter cycle that is when BIDIR 0 and the counter is cleared to zero upon reaching it limit condition when BIDIR 1 and the counter counts down to 0 In either case reloading does not occur if the corresponding NORELOAD bit is set in the CFG register Table 405 SCTimer PWM ma...

Page 400: ...asked regardless of the current state In simple applications that do not use states writing 0x01 or any other value with a 1 in bit 0 will enable the event Since the state doesn t change that is the state variable always remains at its reset value of 0 setting bit 0 permanently enables this event Conversely clearing bit 0 will disable the event Table 407 SCTimer PWM match reload registers 0 to 7 M...

Page 401: ... value If more than one event associated with the same counter occurs in a given clock cycle only the state change specified for the highest numbered event among them takes place Other actions dictated by any simultaneously occurring events all take place Table 409 SCTimer PWM event state mask registers 0 to 7 EV 0 7 _STATE offset 0x300 EV0_STATE to 0x338 EV7_STATE bit description Bit Symbol Descr...

Page 402: ...ate selected by HEVENT when this event is the highest numbered event occurring for that state 0 0 STATEV value is added into STATE the carry out is ignored 1 STATEV value is loaded into STATE 19 15 STATEV This value is loaded into or added to the state selected by HEVENT depending on STATELD when this event is the highest numbered event occurring for that state If STATELD and STATEV are both zero ...

Page 403: ...in bi directional mode depending on the setting of the SETCLRn field in the OUTPUTDIRCTRL register To define the creation of the actual event s that sets an output a match an I O pin toggle etc see the EVn_CTRL register Remark If the SCTimer PWM is operating as two 16 bit counters events can only modify the state of the outputs when neither counter is halted This is true regardless of what trigger...

Page 404: ...7 2 Capture logic 21 7 3 Event selection State variables allow control of the SCTimer PWM across more than one cycle of the counter Counter matches input output edges and state values are combined into a set of general purpose events that can switch outputs request interrupts and change state values Fig 45 Match logic RXQWHU RXQWHU 21 81 0 7 5 LB 0 7 5 LB 0 7 LB 0 7 LB 0DWFK L 0DWFK L Fig 46 Captu...

Page 405: ... each particular state In a multi state SCTimer PWM the SCTimer PWM can change from one state to another state when a user defined event triggers a state change The state change is triggered through each event s EV_CTRL register in one of the following ways The event can increment the current state number by a new value The event can write a new state value Fig 47 Event selection LQSXWV VHOHFW RXW...

Page 406: ...passed since the abort event while no new events are allowed to occur Since multiple states any state number between the maximum implemented state and 31 are locked states multiple abort or error events can be defined each incrementing the state number by a different value 21 7 6 Interrupt generation The SCTimer PWM generates one interrupt to the NVIC 21 7 7 Clearing the prescaler When enabled by ...

Page 407: ...t edge selected by the CLKSEL field is detected The counter is enabled when the prescaler is enabled and PRELIM 0 or the prescaler is equal to the value in PRELIM An I O component of an event can occur in any SCTimer PWM clock when its counter HALT bit is 0 In general a Match component of an event can only occur in an SCTimer PWM clock when its counter HALT and STOP bits are both 0 and the counter...

Page 408: ... new set of events resulting in different actions of the SCTimer PWM Through multiple cycles of the counter events can change the state multiple times and thus create a large variety of event controlled transitions on the SCTimer PWM outputs and or interrupts Once configured the SCTimer PWM can run continuously without software intervention and can generate multiple output patterns entirely under ...

Page 409: ...n the SCTimer PWM outputs in the OUTn_SET or OUTn_CLR registers up to 4 outputs one register per output For each SCTimer PWM output select which events set or clear this output More than one event can change the output and each event can change multiple outputs 3 Define how each event affects the counter Set the corresponding event bit in the LIMIT register for the event to set an upper limit for ...

Page 410: ...ct of set and clear of an output can be made to depend on whether the counter is counting up or down by writing to the OUTPUTDIRCTRL register 21 7 11 Run the SCTimer PWM 1 Configure the SCTimer PWM see Section 21 7 10 Configure the SCTimer PWM 2 Write to the STATE register to define the initial state By default the initial state is state 0 3 To start the SCTimer PWM write to the CTRL register Clea...

Page 411: ... STATELD and STATEV fields in the EVCTRL registers for each event Write 0x1 to the EVn_STATE register of each event Writing 0x1 enables the event In effect the event is allowed to occur in a single state which never changes while the counter is running 21 7 13 SCTimer PWM PWM Example Figure 50 shows a simple application of the SCTimer PWM using two sets of match events EV0 1 and EV3 4 to set clear...

Page 412: ...es unidirectional counter BIDIR_L 0 Clock base CONFIG Uses default values for clock configuration Match Capture registers REGMODE Configure one match register for each match event by setting REGMODE_L bits 0 1 2 3 4 to 0 This is the default Define match values MATCH0 1 2 3 4 Set a match value MATCH0 1 2 4 5_L in each register The match 0 register serves as an automatic limit event that resets the ...

Page 413: ...match register 0 to qualify the event Define how event 5 changes the state EV5_CTRL Set STATEV bits to 0 and the STATED bit to 1 Event 5 changes the state to state 0 Define by which events output 0 is set OUT0_SET Set SET0 bits 0 for event 0 and 3 for event 3 to one to set the output when these events 0 and 3 occur Define by which events output 0 is cleared OUT0_CLR Set CLR0 bits 1 for events 1 an...

Page 414: ... operation Once enabled requires a hardware reset or a Watchdog reset to be disabled Incorrect feed sequence causes immediate watchdog event if enabled The watchdog reload value can optionally be protected such that it can only be changed after the warning interrupt time is reached Flag to indicate Watchdog reset The Watchdog clock WDCLK source is the WatchDog oscillator The Watchdog timer can be ...

Page 415: ...Watchdog consists of a fixed divide by 4 pre scaler and a 24 bit counter which decrements when clocked The minimum value from which the counter decrements is 0xFF Setting a value lower than 0xFF causes 0xFF to be loaded in the counter Hence the minimum Watchdog interval is TWDCLK 256 4 and the maximum Watchdog interval is TWDCLK 224 4 in multiples of TWDCLK 4 The Watchdog should be used in the fol...

Page 416: ...g interrupt the interrupt will occur when the counter matches the value defined by the WARNINT register 22 5 1 Block diagram The block diagram of the Watchdog is shown below in the Figure 52 The synchronization logic PCLK WDCLK is not shown in the block diagram 22 5 2 Clocking and power control The watchdog timer block uses two clocks PCLK and WDCLK PCLK is used for the APB accesses to the watchdo...

Page 417: ... selected watchdog clock WDCLK 22 5 3 Using the WWDT lock features The WWDT supports several lock features which can be enabled to ensure that the WWDT is running at all times Disabling the WWDT clock source Changing the WWDT reload value 22 5 3 1 Disabling the WWDT clock source If bit 5 in the WWDT MOD register is set the WWDT clock source is locked and can not be disabled either by software or b...

Page 418: ...8 Watchdog feed sequence register Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC NA Table 419 TV RO 0x00C Watchdog timer value register This 24 bit register reads out the current value of the Watchdog timer 0xFF Table 420 0x010 Reserved WARNINT R W 0x014 Watchdog Warning Interrupt compare value 0 Table 421 WINDOW R W 0x018 Watchdog Window...

Page 419: ...running in Sleep Deep sleep modes and Power down modes If a watchdog interrupt occurs in Sleep Deep sleep mode or Power down mode and the WWDT interrupt is enabled in the NVIC the device will wake up Note that in Deep sleep and Power down modes the WWDT interrupt must be enabled in the STARTERP1 register in addition to the NVIC See the following registers Table 169 Start logic 1 interrupt wake up ...

Page 420: ... Watchdog is enabled and sets the WDTOF flag The reset will be generated during the second PCLK following an incorrect access to a Watchdog register during a feed sequence It is good practice to disable interrupts around a feed sequence if the application is such that an interrupt might result in rescheduling processor control away from the current task in the middle of the feed and then lead to s...

Page 421: ...dog timer counts 4 096 watchdog clocks for the interrupt to occur prior to a watchdog event If WARNINT is 0 the interrupt will occur at the same time as the watchdog event 22 6 6 Watchdog Timer Window register The WINDOW register determines the highest WDTV value allowed when a watchdog feed is performed If a feed sequence occurs when WDTV is greater than the value in WINDOW a watchdog event will ...

Page 422: ... 31 24 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined NA Fig 53 Early watchdog feed with windowed mode enabled 125A 1258 1259 1257 WDCLK 4 Watchdog Counter Early Feed Event Watchdog Reset Conditions WINDOW 0x1200 WARNINT 0x3FF TC 0x2000 Fig 54 Correct watchdog feed with windowed mode enabled Correct Feed Event 1201 11FF 1200 WDCLK 4 ...

Page 423: ... 9 Table 146 to enable the clock to the register interface Clear the WKT reset using the PRESETCTRL register Table 148 The WKT interrupt is connected to interrupt 15 in the NVIC See Table 108 Enable the low power oscillator in the PMU Table 293 Enable the FRO and FRO output in the PDRUNCFG register if used as the clock source for the timer Table 172 To use an external clock source for the self wak...

Page 424: ...equence When the counter is being used as a wake up timer this write can occur just prior to entering a reduced power mode When a starting count value is loaded the self wake up timer automatically turns on counts from the pre loaded value down to zero generates an interrupt and or a wake up request and then turns itself off until re launched by a subsequent software write 23 5 1 WKT clock sources...

Page 425: ...de is entered An external clock on the WKTCLKIN pin can be used to time the self wake up timer in all low power modes including deep power down 23 6 Register description 23 6 1 Control register The WKT interrupt must be enabled in the NVIC to wake up the part using the self wake up counter Table 423 Register overview WKT base address 0x4000 8000 Name Access Address offset Description Reset value R...

Page 426: ...quest which can wake up the part from any reduced power mode including Deep power down if the clock source is the low power oscillator Writing a 1 clears this status bit 2 CLEARCTR Clears the self wake up timer 0 0 No effect Reading this bit always returns 0 1 Clear the counter Counting is halted until a new count value is loaded 3 SEL_EXTCLK Select external or internal clock source for the self w...

Page 427: ...Table 146 to enable the clock to the register interface Clear the MRT reset using the PRESETCTRL register Table 148 The global MRT interrupt is connected to interrupt 10 in the NVIC 24 4 Pin description The MRT has no configurable pins 24 5 General description The Multi Rate Timer MRT provides a repetitive interrupt timer with four channels Each channel can be programmed with an independent time i...

Page 428: ...and the timer starts to count down again While the timer is running in repeat interrupt mode you can perform the following actions Change the interval value on the next timer cycle by writing a new value 0 to the INTVALn register and setting the LOAD bit to 0 An interrupt is generated when the timer reaches zero On the next cycle the timer counts down from the new value Change the interval value o...

Page 429: ...AD bit to 1 The timer immediately stops counting and moves to the idle state No interrupt is generated when the INTVALn register is updated 24 5 3 One shot bus stall mode The one shot bus stall mode stalls the bus interface for IVALUE 3 cycles of the system clock For the Cortex M0 this mode effectively stops all CPU activity until the MRT has finished counting down to zero At the end of the count ...

Page 430: ...gister 0 Table 427 TIMER1 R W 0x14 MRT1 Timer register This register reads the value of the down counter 0x7FFF FFFF Table 428 CTRL1 R W 0x18 MRT1 Control register This register controls the MRT1 modes 0 Table 429 STAT1 R W 0x1C MRT1 Status register 0 Table 430 INTVAL2 R W 0x20 MRT2 Time interval value register This value is loaded into the TIMER2 register 0 Table 427 TIMER2 R W 0x24 MRT2 Timer re...

Page 431: ...he following If LOAD 1 the timer stops immediately If LOAD 0 the timer stops at the end of the time interval 0 31 LOAD Determines how the timer interval value IVALUE 1 is loaded into the TIMERn register This bit is write only Reading this bit always returns 0 0 0 No force load The load from the INTVALn register to the TIMERn register is processed at the end of the time interval if the repeat mode ...

Page 432: ...e 429 Control register CTRL 0 3 address 0x4000 4008 CTRL0 to 0x4000 4038 CTRL3 bit description Bit Symbol Value Description Reset value 0 INTEN Enable the TIMERn interrupt 0 0 Disable 1 Enable 2 1 MODE Selects timer mode 0 0x0 Repeat interrupt mode 0x1 One shot interrupt mode 0x2 One shot bus stall mode 0x3 Reserved 31 3 Reserved 0 Table 430 Status register STAT 0 3 address 0x4000 400C STAT0 to 0x...

Page 433: ...egister is also set to 1 the interrupt for timer channel 0 and the global interrupt are raised Writing a 1 to this bit clears the interrupt request 1 GFLAG1 Monitors the interrupt flag of TIMER1 0 0 No pending interrupt Writing a zero is equivalent to no operation 1 Pending interrupt The interrupt is pending because TIMER1 has reached the end of the time interval If the INTEN bit in the CONTROL1 r...

Page 434: ...k is fixed to half of the system clock frequency 2 Enable the clock source for the SysTick timer in the SYST_CSR register Table 434 3 The calibration value of the SysTick timer is contained in the SYSTCKCAL register in the system configuration block SYSCON see Table 164 25 4 Pin description The SysTick has no configurable pins 25 5 General description The block diagram of the SysTick timer is show...

Page 435: ... and status register can be used to determine if an action completed within a set duration as part of a dynamic clock management control loop Refer to Ref 6 for details 25 6 Register description The SysTick timer registers are located on the ARM Cortex M0 private peripheral bus see Figure 2 and are part of the ARM Cortex M0 core peripherals For details see Ref 6 1 Reset Value reflects the data sto...

Page 436: ...ed When enabled the interrupt is generated when the System Tick counter counts down to 0 0 2 CLKSOURCE System Tick clock source selection When 1 the system clock CPU clock is selected When 0 the system clock 2 is selected as the reference clock 0 15 3 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined NA 16 COUNTFLAG Returns 1 if the Sys...

Page 437: ...YST_CALIB register and may be changed by software 25 7 1 Example timer calculation To use the system tick timer do the following 1 Program the SYST_RVR register with the reload value RELOAD to obtain the desired time interval 2 Clear the SYST_CVR register by writing to it This ensures that the timer will count from the SYST_RVR value rather than an arbitrary value when the timer is enabled 3 Progr...

Page 438: ...mode 26 3 Basic configuration Configure the ADC as follows Use the PDRUNCFG register to power the ADC See Table 172 Once the ADC is powered by the PDRUNCFG register bit the low power mode bit in the ADC CTRL register can be used to turn off the ADC when it is not sampling and turn on the ADC automatically when any of the ADC conversion triggers are raised See Table 443 and Section 26 7 5 Use the S...

Page 439: ...e SEQ_ENA and the START bits Be careful not to modify the TRIGGER TRIGPOL and SEQ_ENA bits on subsequent writes to the START bit See also Section 26 7 2 1 Avoiding spurious hardware triggers The ADC converts an analog input signal VIN on the ADC_ 11 0 The VREFP and VREFN pins provide a positive and negative reference voltage input The result of the conversion is 4095 x VIN VREFN VREFP VREFN The re...

Page 440: ...rupt block for level sensitive and active high on pin interrupt 0 and enable it LPC_PIN_INT ISEL 0x1 level sensitive LPC_PIN_INT IENF 0x1 active high LPC_PIN_INT SIENR 0x1 enabled 6 Select PININT0_IRQ by writing 0x1 to the TRIGGER bits in the SEQA_CTRL register 7 To generate one interrupt at the end of the entire sequence set the MODE bit to 1 in the SEQA_CTRL register 8 Select single step mode by...

Page 441: ... restore the contents of the CTRL register or use the default values A calibration cycle requires approximately 290 μs to complete While calibration is in progress normal ADC conversions cannot be launched and the ADC Control Register must not be written to The calibration procedure does not use the CPU or memory so other processes can be executed during calibration 26 4 Pin description The ADC ce...

Page 442: ...pin whenever a digital function is selected on that pin Table 440 ADC supply and reference voltage pins Function Description VREFP Positive voltage reference The VREFP voltage level must be between 2 4 V and VDDA For best performance select VREFP VDDA and VREFN VSSA VREFN Negative voltage reference VDDA VDD The analog supply voltage is internally connected to VDD VSSA VSS ADC ground is internally ...

Page 443: ... ADC runs through the pre defined conversion sequence converting a sample whenever a trigger signal arrives until the sequence is disabled The ADC controller uses the system clock as a bus clock The ADC clock is derived from the system clock A programmable divider is included to scale the system clock to the maximum ADC clock rate of 30 MHz The ADC clock drives the successive approximation process...

Page 444: ...annel 1 Data Register This register contains the result of the most recent conversion completed on channel 1 NA Table 448 DAT2 RO 0x028 A D Channel 2 Data Register This register contains the result of the most recent conversion completed on channel 2 NA Table 448 DAT3 RO 0x02C A D Channel 3 Data Register This register contains the result of the most recent conversion completed on channel 3 NA Tabl...

Page 445: ...mparison for any channels linked to threshold pair 0 0x0 Table 451 THR1_HIGH R W 0x05C A D High Compare Threshold Register 1 Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1 0x0 Table 452 CHAN_THRSEL R W 0x060 A D Channel Threshold Select Register Specifies which set of threshold compare registers are to be used for each channel 0x0 ...

Page 446: ...t in certain cases such as a high impedance analog source a slower clock may be desirable 0 9 8 Reserved Do not write a one to these bits 0 10 LPWRMODE Select low power ADC mode The analog circuitry is automatically powered down when no conversions are taking place When any hardware or software triggering event is detected the analog circuitry is enabled After the required start up time the reques...

Page 447: ...t bit 31 is low It is safe to change this field and set bit 31 in the same write 0 0 Negative edge A negative edge launches the conversion sequence on the selected trigger input 1 Positive edge A positive edge launches the conversion sequence on the selected trigger input 19 SYNCBYPASS Setting this bit allows the hardware trigger input to bypass synchronization flip flops stages and therefore shor...

Page 448: ...s sequence and launch a B sequence in it s place The conversion currently in progress will be terminated The A sequence that was interrupted will automatically resume after the B sequence completes The channel whose conversion was terminated will be re sampled and the conversion sequence will resume from that point 30 MODE Indicates whether the primary method for retrieving conversion results for ...

Page 449: ...d If this bit is cleared while sequence A is in progress the sequence will be halted at the end of the current conversion After the sequence is re enabled a new trigger will be required to restart the sequence beginning with the next enabled channel 1 Enabled Sequence A is enabled Table 444 A D Conversion Sequence A Control Register SEQA_CTRL address 0x4001 C008 bit description Bit Symbol Value De...

Page 450: ...or not a trigger pulse must be maintained for at least one system clock period Asynchronous mode Synchronization may be bypassed this bit may be set if it is certain that the duration of a trigger input pulse will be at least one cycle of the ADC clock regardless of whether the trigger comes from and on chip or off chip source If this bit is NOT set the trigger pulse must at least be maintained fo...

Page 451: ...run interrupt as described below 0 0 End of conversion The sequence B interrupt DMA flag will be set at the end of each individual A D conversion performed under sequence B This flag will mirror the DATAVALID bit in the SEQB_GDAT register The OVERRUN bit in the SEQB_GDAT register will contribute to generation of an overrun interrupt if enabled 1 End of sequence The sequence B interrupt DMA flag wi...

Page 452: ...it in the corresponding ADSEQn_CTRL register since this will impact interrupt and overrun flag generation Table 446 A D Sequence A Global Data Register SEQA_GDAT address 0x4001 C010 bit description Bit Symbol Description Reset value 3 0 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined NA 15 4 RESULT This field contains the 12 bit A D c...

Page 453: ...4001 C014 bit description Bit Symbol Description Reset value 3 0 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined NA 15 4 RESULT This field contains the 12 bit A D conversion result from the most recent conversion performed under conversion sequence associated with this register This will be a binary fraction representing the voltage o...

Page 454: ...signated LOW threshold register THRn_LOW as did the previous conversion on this channel 0x1 Reserved 0x2 Downward Threshold Crossing Detected Indicates that a threshold crossing in the downward direction has occurred i e the previous sample on this channel was above the threshold value established by the designated LOW threshold register THRn_LOW and the current sample is below that threshold 0x3 ...

Page 455: ...ion was greater than or equal to the value programmed into the designated LOW threshold register THRn_LOW but less than or equal to the value programmed into the designated HIGH threshold register THRn_HIGH 0x1 Below Range The last completed conversion on was less than the value programmed into the designated LOW threshold register THRn_LOW 0x2 Above Range The last completed conversion was greater...

Page 456: ...ticular register relates to i e this field will contain 0b0000 for the DAT0 register 0b0001 for the DAT1 register etc NA 30 OVERRUN This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read i e while the DONE bit is set This bit is cleared along with the DONE bit whenever this register is read or when ...

Page 457: ...rved user software should not write ones to reserved bits The value read from a reserved bit is not defined NA 15 4 THRLOW Low threshold value against which A D results will be compared 0x000 31 16 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined NA Table 450 A D Compare Low Threshold register 1 THR1_LOW address 0x4001 C054 bit descrip...

Page 458: ...sters 1 CH1_THRSEL Threshold select by channel 0 0 Threshold 0 Channel 1 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers 1 Threshold 1 Channel 1 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers 2 CH2_THRSEL Threshold select by channel 0 0 Threshold 0 Channel 2 results will be compared aga...

Page 459: ...sults will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers 8 CH8_THRSEL Threshold select by channel 0 0 Threshold 0 Channel 8 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers 1 Threshold 1 Channel 8 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers...

Page 460: ...sabled The sequence A interrupt DMA trigger is disabled 1 Enabled The sequence A interrupt DMA trigger is enabled and will be asserted either upon completion of each individual conversion performed as part of sequence A or upon completion of the entire A sequence of conversions depending on the MODE bit in the SEQA_CTRL register 1 SEQB_INTEN Sequence B interrupt enable 0 0 Disabled The sequence B ...

Page 461: ... 0x2 Crossing threshold 0x3 Reserved 14 13 ADCMPINTEN5 Threshold comparison interrupt enable 00 0x0 Disabled 0x1 Outside threshold 0x2 Crossing threshold 0x3 Reserved 16 15 ADCMPINTEN6 Threshold comparison interrupt enable 00 0x0 Disabled 0x1 Outside threshold 0x2 Crossing threshold 0x3 Reserved 18 17 ADCMPINTEN7 Threshold comparison interrupt enable 00 0x0 Disabled 0x1 Outside threshold 0x2 Cross...

Page 462: ...user software should not write ones to reserved bits The value read from a reserved bit is not defined NA Table 454 A D Interrupt Enable register INTEN address 0x4001 C064 bit description Bit Symbol Value Description Reset value Table 455 A D Flags register FLAGS address 0x4001 C068 bit description Bit Symbol Description Reset value 0 THCMP0 Threshold comparison event on Channel 0 Set to 1 upon ei...

Page 463: ...for A D channel 0 0 13 OVERRUN1 Mirrors the OVERRRUN status flag from the result register for A D channel 1 0 14 OVERRUN2 Mirrors the OVERRRUN status flag from the result register for A D channel 2 0 15 OVERRUN3 Mirrors the OVERRRUN status flag from the result register for A D channel 3 0 16 OVERRUN4 Mirrors the OVERRRUN status flag from the result register for A D channel 4 0 17 OVERRUN5 Mirrors ...

Page 464: ...of an entire B sequence In this case it must be cleared by writing a 1 to this SEQB_INT bit This interrupt must be enabled in the INTEN register 0 30 THCMP_INT Threshold Comparison Interrupt DMA flag This bit will be set if any of the 12 THCMP flags in the lower bits of this register are set to 1 due to an enabled out of range or threshold crossing event on any channel Each type of threshold compa...

Page 465: ...the alternate conversion sequence is already in progress except in the case of a B trigger interrupting an A sequence if the A sequence is set to LOWPRIO If any of these conditions is true the new trigger event will be ignored and will have no effect In addition if the single step bit for a sequence is set each new trigger will cause a single conversion to be performed on the next channel in the s...

Page 466: ...TRL register is set to 1 and a software or hardware trigger for the B sequence occurs then the burst will be immediately interrupted and a B sequence will be initiated The interrupted A sequence will resume continuous cycling starting with the aborted conversion after the alternate sequence has completed 26 7 4 Interrupts There are four interrupts that can be generated by the ADC Conversion Comple...

Page 467: ...ta registers are cleared when data related to that channel is read from either of the global data registers as well as when the individual data registers themselves are read 26 7 5 Optional operating modes The following optional mode of A D operation may be selected in the CTRL register Low power mode When this mode is selected the analog portions of the ADC are automatically shut down when no con...

Page 468: ...0 16 June 2017 468 of 515 NXP Semiconductors UM11029 Chapter 26 LPC84x 12 bit Analog to Digital Converter ADC 26 7 7 Hardware Trigger Source Selection Each ADC has a selection of several on chip and off chip hardware trigger sources The trigger to be used for each conversion sequence is specified in the TRIGGER fields in the two SEQn_CTRL registers ...

Page 469: ... enable the clock to the DAC register interface See Section 8 6 21 3 Pins Enable the DAC fixed pin function in the relevant SWM PINENABLE register and also set the DACENABLE bit in the relevant IOCON register 4 DMA The DAC can be connected to the DMA controller see Section 27 5 2 For DMA connections 27 2 Features 10 bit digital to analog converter Resistor string architecture Buffered output Power...

Page 470: ...et_intrpt pbus pbus_wr_to_CR DMA_ena intrptDMA_req Table 457 D A Pin Description Pin Type Description DAC_OUT Output Analog Output After the selected settling time after the CR is written with a new value the voltage on this pin with respect to VSSA is VALUE VREFP 1024 Note that DAC_OUT is disabled when the CPU is in Deep sleep Power down or Deep Power down modes VREFP Reference Voltage Reference ...

Page 471: ...s the reload value for the DAC DMA Interrupt timer 0 461 Table 459 D A Converter Register CR address 0x4001 4000 DAC0 0x4001 8000 DAC1 bit description Bit Symbol Value Description Reset Value 5 0 Reserved Read value is undefined only zero should be written NA 15 6 VALUE After the selected settling time after this field is written with a new VALUE the voltage on the DAC_OUT pin with respect to VSSA...

Page 472: ...l be enabled Writes to the CR register are written to a pre buffer and then transferred to the CR on the next time out of the counter 2 CNT_ENA Time out counter operation 0 0 Disable 1 Enable 3 DMA_ENA DMA access 0 0 Disable 1 Enable DMA Burst Request Input 7 is enabled for the DAC see Table 690 31 4 Reserved Read value is undefined only zero should be written NA Table 460 D A Control register CTR...

Page 473: ...accessible but the timer itself is not accessible for either read or write If the DMA_ENA bit is set in the DACCTRL register the DAC DMA request will be routed to the GPDMA When the DMA_ENA bit is cleared the default state after a reset DAC DMA requests are blocked 27 6 2 Double buffering Double buffering is enabled only if both the CNT_ENA and the DBLBUF_ENA bits are set in DACCTRL In this case a...

Page 474: ...log comparator through the PDRUNCFG register Table 172 Clear the analog comparator peripheral reset using the PRESETCTRL register Table 148 The analog comparator interrupt is connected to interrupt 11 in the NVIC Configure the analog comparator pin functions through the switch matrix See Section 28 4 28 3 1 Connect the comparator output to the SCTimer PWM The comparator output function ACMP_O can ...

Page 475: ...onnect an internal signal to a package pin to assign the analog comparator output to any pin on the LPC84x package 28 5 General description The analog comparator can compare voltage levels on external pins and internal voltages The comparator has seven inputs multiplexed separately to its positive and negative inputs The multiplexers are controlled by the comparator register CTL see Figure 63 and ...

Page 476: ...changed and when either or both voltage sources are changed Software can deal with these factors by repeatedly reading the comparator output until a number of readings yield the same result 28 5 3 Interrupts The interrupt output comes from edge detection circuitry in this module Rising edges falling edges or both edges can set the COMPEDGE bit and thus request an interrupt COMPEDGE and the interru...

Page 477: ... Section 28 3 1 Connect the comparator output to the SCTimer PWM 28 6 Register description 28 6 1 Comparator control register This register enables the comparator configures the interrupts and controls the input multiplexers on both sides of the comparator All bits not shown in Table 464 are reserved and should be written as 0 Table 463 Register overview Analog comparator base address 0x4002 4000 ...

Page 478: ...ved Write as 0 0 20 EDGECLR Interrupt clear bit To clear the COMPEDGE bit and thus negate the interrupt request toggle the EDGECLR bit by first writing a 1 and then a 0 0 21 COMPSTAT Comparator status This bit reflects the state of the comparator output 0 22 Reserved Write as 0 0 23 COMPEDGE Comparator edge detect status 0 24 INTENA Must be set to generate interrupts 1 26 25 HYS Controls the hyste...

Page 479: ...e ladder The fraction of the reference voltage produced by the ladder is programmable in steps of 1 31 Table 465 Voltage ladder register LAD address 0x4002 4004 bit description Bit Symbol Value Description Reset value 0 LADEN Voltage ladder enable 0 5 1 LADSEL Voltage ladder value The reference voltage Vref depends on the LADREF bit below 00000 VSS 00001 1 x Vref 31 00010 2 x Vref 31 11111 Vref 0 ...

Page 480: ...omplement programmable setting for input data and CRC sum Programmable seed number setting Accept any size of data width per write 8 16 or 32 bit 8 bit write 1 cycle operation 16 bit write 2 cycle operation 8 bit x 2 cycle 32 bit write 4 cycle operation 8 bit x 4 cycle 29 3 Basic configuration Enable the clock to the CRC engine in the SYSAHBCLKCTRL register Table 146 bit 13 29 4 Pin description Th...

Page 481: ...ights reserved User manual Rev 1 0 16 June 2017 481 of 515 NXP Semiconductors UM11029 Chapter 29 LPC84x CRC engine Fig 64 CRC block diagram CCIT T POLY CRC 16 POLY CRC 32 POLY CRC REG BIT REVERSE 1 s COMP B3 B2 B1 B0 D E Q CRC FSM 1 s COMP BIT REVERSE CRC SEED CRC MODE MUX MUX MUX AHB BUS CRC I D CRC WR BUF CRC SUM ...

Page 482: ...ecksum register 0x0000 FFFF Table 469 WR_DATA WO 0x008 CRC data register Table 470 Table 467 CRC mode register MODE address 0x5000 0000 bit description Bit Symbol Description Reset value 1 0 CRC_POLY CRC polynom 1X CRC 32 polynomial 01 CRC 16 polynomial 00 CRC CCITT polynomial 00 2 BIT_RVS_WR Data bit order 1 Bit order reverse for CRC_WR_DATA per byte 0 No bit order reverse for CRC_WR_DATA per byt...

Page 483: ...O 1 s complement for data input NO Bit order reverse for CRC sum NO 1 s complement for CRC sum NO CRC_MODE 0x0000 0000 CRC_SEED 0x0000 FFFF Table 468 CRC seed register SEED address 0x5000 0004 bit description Bit Symbol Description Reset value 31 0 CRC_SEED A write access to this register will load CRC seed value to CRC_SUM register with selected bit order and 1 s complement pre processes Remark A...

Page 484: ...Seed Value 0x0000 Bit order reverse for data input YES 1 s complement for data input NO Bit order reverse for CRC sum YES 1 s complement for CRC sum NO CRC_MODE 0x0000 0015 CRC_SEED 0x0000 0000 29 7 3 CRC 32 set up Polynomial x32 x26 x23 x22 x16 x12 x11 x10 x8 x7 x5 x4 x2 x 1 Seed Value 0xFFFF FFFF Bit order reverse for data input YES 1 s complement for data input NO Bit order reverse for CRC sum ...

Page 485: ...tions to overload and operators in C 30 3 General description The API calls to the ROM are performed by executing functions which are pointed by a pointer within the ROM Driver Table Figure 65 shows the pointer structure used to call the Integer divider API UM11029 Chapter 30 LPC84x ROM API integer divide routines Rev 1 0 16 June 2017 User manual Fig 65 ROM pointer structure Ptr to ROM Driver tabl...

Page 486: ...d denominator Unsigned integer division IDIV_RETURN_T sidivmod int numerator int denominator Signed integer division with remainder UIDIV_RETURN_T uidivmod unsigned numerator unsigned denominator Unsigned integer division with remainder ROM_DIV_API_T ROM_DIV_API_T const pROMDiv LPC_ROM_API divApiBase The ROM API table shown in Section 3 5 2 ROM based APIs must be included in the code 30 4 1 DIV si...

Page 487: ...e uidiv Prototype int uidiv int32_t numerator int32_t denominator Input parameter numerator Numerator signed integer denominator Denominator signed integer Return Unsigned division result without remainder Description Unsigned integer division Table 474 sidivmod Routine sidivmod Prototype IDIV_RETURN_T sidivmod int32_t numerator int32_t denominator Input parameter numerator Numerator signed intege...

Page 488: ...ption 30 5 1 Signed division The example C code listing below shows how to perform a signed integer division via the ROM API Divide 99 by 6 int32_t result result pROMDiv sidiv 99 6 result now contains 16 30 5 2 Unsigned division with remainder The example C code listing below shows how to perform an unsigned integer division with remainder via the ROM API Modulus Divide 99 by 4 uidiv_return result...

Page 489: ...or debugging enable the MTB clock in the SYSAHBCLKCTRL register Table 146 Only RAM0 can be used as trace buffer by MTB that means the maximum trace buffer size is 4 KB 31 4 Pin description The SWD functions are assigned to pins through the switch matrix The SWD functions are fixed pin functions that are enabled through the switch matrix and can only be assigned to special pins on the package The S...

Page 490: ...ration of SWD pins entry into Deep power down mode out of reset etc This pin can be used for other functions such as GPIO but it should not be held LOW on power up or reset Table 477 JTAG boundary scan pin description Function Pin name Type Description TCK SWCLK PIO0_3 TCK I JTAG Test Clock This pin is the clock for JTAG boundary scan when the RESET pin is LOW TMS SWDIO PIO0_2 TMS I JTAG Test Mode...

Page 491: ...ternally 3 Wait for at least 250 s 4 Pull the RESET pin LOW externally 5 Perform boundary scan operations 6 Once the boundary scan operations are completed assert the TRST pin to enable the SWD debug mode and release the RESET pin pull HIGH Remark The JTAG interface cannot be used for debug purposes Remark POR BOD reset or a LOW on the TRST pin puts the test TAP controller in the Test Logic Reset ...

Page 492: ...at memory address 0x5000 C000 and are described in Ref 4 The EXTTRACE register in the SYSCON block see Section 8 6 34 starts and stops tracing in conjunction with the TSTARTEN and TSTOPEN bits in the MTB MASTER register The trace is stored in the local SRAM starting at address 0x1000 0000 The trace memory location is configured in the MTB POSITION register Remark The MTB BASE register is not imple...

Page 493: ...ookbook 6 ARMv6 M Architecture Reference Manual UM11029 Chapter 32 Supplementary information Rev 1 0 16 June 2017 User manual Table 478 Abbreviations Acronym Description A D Analog to Digital ADC Analog to Digital Converter AHB Advanced High performance Bus APB Advanced Peripheral Bus BOD BrownOut Detection GPIO General Purpose Input Output JTAG Joint Test Action Group PLL Phase Locked Loop RC Res...

Page 494: ...miconductors products are not designed authorized or warranted to be suitable for use in life support life critical or safety critical systems or equipment nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury death or severe property or environmental damage NXP Semiconductors and its suppliers accept no liability ...

Page 495: ... command 41 Table 42 IAP Read Part Identification command 41 Table 43 IAP Read Boot Code version number command 42 Table 44 IAP Compare command 42 Table 45 Reinvoke ISP 42 Table 46 IAP ReadUID command 43 Table 47 IAP Erase page command 43 Table 48 IAP Read Signature command 43 Table 49 IAP Read FAIM page command 44 Table 50 IAP Write FAIM page command 44 Table 51 ISP commands allowed for different...

Page 496: ... 90 Table 129 System oscillator control register SYSOSCCTRL address 0x4004 8020 bit description 90 Table 130 Watchdog oscillator control register WDTOSCCTRL address 0x4004 8024 bit description 91 Table 131 FRO oscillator control register FROOSCCTRL address 0x4004 8028 bit description 92 Table 132 FRO direct clock source update enable register FRODIRECTCLKUEN address 0x4004 8030 bit description 92 ...

Page 497: ...ency routine 125 Table 178 Movable functions assign to pins PIO0_0 to PIO0_31 and PIO1_0 to PIO1_21 through switch matrix 130 Table 179 Register overview Switch matrix base address 0x4000 C000 133 Table 180 Pin assign register 0 PINASSIGN0 address 0x4000 C000 bit description 134 Table 181 Pin assign register 1 PINASSIGN1 address 0x4000 C004 bit description 135 Table 182 Pin assign register 2 PINAS...

Page 498: ...ddress 0x4004 4094 bit description 186 Table 235 PIO1_2 register PIO1_2 address 0x4004 4098 bit description 187 Table 236 PIO1_14 register PIO1_14 address 0x4004 409C bit description 188 Table 237 PIO1_15 register PIO1_15 address 0x4004 40A0 bit description 189 Table 238 PIO1_3 register PIO1_3 address 0x4004 40A4 bit description 190 Table 239 PIO1_4 register PIO1_4 address 0x4004 40A8 bit descript...

Page 499: ...tive pins 235 Table 283 INPUT MUX pin description 239 Table 284 Register overview Input multiplexing base address 0x4002 C000 241 Table 285 DMA input trigger input mux input registers 0 to 1 DMA_INMUX_INMUX 0 1 address 0x4002 C000 DMA_INMUX_INMUX0 to 0x4002 C004 DMA_INMUX_INMUX1 bit description 243 Table 286 SCT input mux registers 0 to 3 SCT0_INMUX 0 3 address 0x4002 C020 SCT0_INMUX0 to 0x4002 C0...

Page 500: ...9 Table 329 USART Receiver Data with Status register RXDATSTAT address 0x4006 4018 USART0 0x4006 8018 USART1 0x4006 C018 USART2 0x4007 0018 USART3 0x4007 4018 USART4 bit description 299 Table 330 USART Transmitter Data Register TXDAT address 0x4006 401C USART0 0x4006 801C USART1 0x4006 C01C USART2 0x4007 001C USART3 0x4007 401C USART4 bit description 300 Table 331 USART Baud Rate Generator registe...

Page 501: ...R 0 3 address 0x4005 0048 SLVADR0 to 0x4005 0054 SLVADR3 I2C0 0x4005 4048 SLVADR0 to 0x4005 4054 SLVADR3 I2C1 0x4003 0048 SLVADR0 to 0x4003 0054 SLVADR3 I2C2 0x4003 4048 SLVADR0 to 0x4003 4054 SLVADR3 I2C3 bit description 352 Table 366 Slave address Qualifier 0 register SLVQUAL0 address 0x4005 0058 I2C0 0x4005 4058 I2C1 0x4003 0058 I2C2 0x4003 4058 I2C3 bit description 353 Table 367 Monitor data r...

Page 502: ...erview Watchdog timer base address 0x4000 0000 418 Table 416 Watchdog mode register MOD 0x4000 0000 bit description 418 Table 417 Watchdog operating modes selection 420 Table 418 Watchdog Timer Constant register TC 0x4000 0004 bit description 420 Table 419 Watchdog Feed register FEED 0x4000 0008 bit description 421 Table 420 Watchdog Timer Value register TV 0x4000 000C bit description 421 Table 42...

Page 503: ...C06C bit description 464 Table 457 D A Pin Description 470 Table 458 Register overview DAC base address 0x4001 4000 DAC0 0x4001 8000 DAC1 471 Table 459 D A Converter Register CR address 0x4001 4000 DAC0 0x4001 8000 DAC1 bit description 471 Table 460 D A Control register CTRL address 0x4001 4004 DAC0 0x4001 8004 DAC1 bit description 471 Table 461 D A Converter Counter Value register CNTVAL address ...

Page 504: ...draw 307 Fig 28 SPI block diagram 310 Fig 29 Basic SPI operating modes 322 Fig 30 Pre_delay and Post_delay 323 Fig 31 Frame_delay 324 Fig 32 Transfer_delay 325 Fig 33 Examples of data stalls 328 Fig 34 I2C clocking need to draw 330 Fig 35 I2C block diagram 336 Fig 36 32 bit counter timer block diagram 359 Fig 37 A timer cycle in which PR 2 MRx 6 and both interrupt and reset on match are enabled 37...

Page 505: ... 21 5 2 Features 21 5 3 General description 21 5 3 1 Boot loader 21 5 3 2 Memory map after any reset 21 5 3 3 Flash content protection mechanism 22 5 3 4 Criteria for Valid User Code 22 5 3 5 Flash partitions 22 5 3 6 Code Read Protection CRP 23 5 3 6 1 ISP entry protection 24 5 3 6 2 ISP entry configuration and detection 24 5 3 7 ISP interrupt and SRAM use 25 5 3 7 1 Interrupts during IAP 25 5 3 ...

Page 506: ...mmand 55 5 8 15 SH_CMD_WRITE_RAM 0xB0 command 56 5 8 16 SH_CMD_GOTO 0xB1 command 57 5 8 17 SH_CMD_FAIM_READ 0xBE command 57 5 8 18 SH_CMD_FAIM_WRITE 0xBF command 58 5 8 19 I2C SPI ISP Error codes 58 5 8 20 I2C SPI ISP mode protocol software support 58 Chapter 6 LPC84x Flash signature generator 6 1 How to read this chapter 61 6 2 Features 61 6 3 General description 61 6 4 Register description 61 6 ...

Page 507: ...6 22 System clock control 1 register 100 8 6 23 Peripheral reset control 0 register 100 8 6 24 Peripheral reset control 1 register 102 8 6 25 Peripheral clock source select registers 104 8 6 26 Fractional generator 0 divider value register 104 8 6 27 Fractional generator 0 multiplier value register 105 8 6 28 FRG0 clock source select register 106 8 6 29 Fractional generator 1 divider value registe...

Page 508: ...in mode 146 11 4 4 Open drain mode 147 11 4 5 Analog mode 147 11 4 6 I2C bus mode 147 11 4 7 Programmable digital filter 147 11 5 Register description 148 11 5 1 PIO0_17 register 151 11 5 2 PIO0_13 register 152 11 5 3 PIO0_12 register 153 11 5 4 PIO0_5 register 154 11 5 5 PIO0_4 register 155 11 5 6 PIO0_3 register 156 11 5 7 PIO0_2 register 157 11 5 8 PIO0_11 register 158 11 5 9 PIO0_10 register 1...

Page 509: ...ription 215 13 5 1 Pin interrupts 216 13 5 2 Pattern match engine 216 13 5 2 1 Inputs and outputs of the pattern match engine 218 13 5 2 2 Boolean expressions 219 13 6 Register description 220 13 6 1 Pin interrupt mode register 220 13 6 2 Pin interrupt level or rising edge interrupt enable register 221 13 6 3 Pin interrupt level or rising edge interrupt set register 221 13 6 4 Pin interrupt level ...

Page 510: ... 7 7 2 Programming deep power down mode using the WAKEUP or RESET pin 258 15 7 7 3 Wake up from deep power down mode using the WAKEUP pin or RESET pin 258 15 7 7 4 Programming deep power down mode using the self wake up timer 258 15 7 7 5 Wake up from deep power down mode using the self wake up timer 259 Chapter 16 LPC84x DMA controller 16 1 How to read this chapter 260 16 2 Features 260 16 3 Basi...

Page 511: ...Features 306 18 3 Basic configuration 306 18 3 1 Configure the SPI for wake up 307 18 3 1 1 Wake up from Sleep mode 308 18 3 1 2 Wake up from Deep sleep or Power down mode 308 18 4 Pin description 308 18 5 General description 310 18 6 Register description 310 18 6 1 SPI Configuration register 311 18 6 2 SPI Delay register 312 18 6 3 SPI Status register 314 18 6 4 SPI Interrupt Enable read and Set ...

Page 512: ...0 7 8 Capture Control Register 365 20 7 9 Capture Registers 366 20 7 10 External Match Register 366 20 7 11 Count Control Register 368 20 7 12 PWM Control Register 369 20 7 13 Match Shadow Registers 370 20 8 Functional description 371 20 8 1 Rules for single edge controlled PWM outputs 371 20 8 2 DMA operation 372 Chapter 21 LPC84x SCTimer PWM 21 1 How to read this chapter 373 21 2 Features 373 21...

Page 513: ...tes 410 21 7 10 5 Miscellaneous options 410 21 7 11 Run the SCTimer PWM 410 21 7 12 Configure the SCTimer PWM without using states 411 21 7 13 SCTimer PWM PWM Example 411 Chapter 22 LPC84x Windowed Watchdog Timer WWDT 22 1 How to read this chapter 414 22 2 Features 414 22 3 Basic configuration 414 22 4 Pin description 415 22 5 General description 415 22 5 1 Block diagram 416 22 5 2 Clocking and po...

Page 514: ...ntrol Register 449 26 6 4 A D Global Data Register A and B 452 26 6 5 A D Channel Data Registers 0 to 11 454 26 6 6 A D Compare Low Threshold Registers 0 and 1 456 26 6 7 A D Compare High Threshold Registers 0 and 1 457 26 6 8 A D Channel Threshold Select register 458 26 6 9 A D Interrupt Enable Register 459 26 6 10 A D Flag register 462 26 6 11 A D trim register 464 26 7 Functional description 46...

Page 515: ...a register 483 29 7 Functional description 483 29 7 1 CRC CCITT set up 483 29 7 2 CRC 16 set up 484 29 7 3 CRC 32 set up 484 Chapter 30 LPC84x ROM API integer divide routines 30 1 How to read this chapter 485 30 2 Features 485 30 3 General description 485 30 4 API description 486 30 4 1 DIV signed integer division 486 30 4 2 DIV unsigned integer division 487 30 4 3 DIV signed integer division with...

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