NXP Semiconductors LPC43Sxx, User Manual

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UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2015. All rights reserved.
User manual Rev. 2.1 — 10 December 2015 210 of 1441
14.1 How to read this chapter
The ADCHS is only available on parts LPC4370/LPC43S70.
The Cortex-M0 subsystem core and the subsystem AHB multilayer matrix are only
enabled on parts LPC4370/LPC43S70 and LPC436x/LPC43S6x.
Flash/EEPROM, Ethernet, USB0, USB1, and LCD-related clocks are not available on all
parts and packages. See
Table 2 .
14.2 Basic configuration
The CCU1/2 are configured as follows:
•
See Table 155 for clocking and power control.
•
All branch clocks are enabled by default.
•
Do not reset the CCUs during normal operation.
•
Configure the output clock for the EMC clock divider ( Table 164 ) together with bit 16 in
the CREG6 register ( Table 105 ).
Remark: The CCU registers for a given branch clock are only read and write accessible
when the branch clock is enabled.
14.3 Features
The CCUs switch the clocks to individual peripherals on or off.
•
Auto mode activates the AHB disable protocol before switching off the branch clock.
•
In Wake-up mode, clocks can be selected to run automatically after a wake-up event.
14.4 General description
Each CGU base clock has several clock branches which can be turned on or off
independently by the Clock Control Units CCU1 or CCU2. The branch clocks are
distributed between CCU1 and CCU2.
UM10503
Chapter 14: LPC43xx/LPC43Sxx Clock Control Unit (CCU)
Rev. 2.1 — 10 December 2015 User manual
Table 155. CCU clocking and power control
Base clock Branch clock Operating frequency
CCU1 BASE_M4_CLK CLK_M4_BUS up to 204 MHz
CCU2 BASE_M4_CLK CLK_M4_BUS up to 204 MHz