UM10208_2
© NXP B.V. 2007. All rights reserved.
User manual
Rev. 02 — 1 June 2007
81 of 362
NXP Semiconductors
UM10208
Chapter 7: LPC2800 CGU
EMCESR1 = CGU_ESR_FD0; /* Select spreading stage EMC_CLK2, external memory controller */
MMIOESR1 = CGU_ESR_FD0; /* Select spreading stage MMIO_CLK, main clock for interrupt controller */
MCIESR1 = CGU_ESR_FD1; /* Select spreading stage MCI_MCLK, MCI clock for SD/MCI interface */
LCDESR1 = CGU_ESR_FD3; /* Select spreading stage LCD_CLK, LCD bus clock for LCD interface */
CPUESR0 = 0x0; /* The same as the SYS base clock */
/* Configuration of power control register */
CPUPCR2 |= CGU_PCR_ENOUT_EN /* Set ENOUT_EN bit such that CPU_CLK ( main processor clock ) */
/* can be higher than CPU_GCLK ( gated HCLK for processor registers ) */
/* Configuration of base control register */
SYSBCR = CGU_BCR_FDRUN; /* Start fractional dividers */
5.3 Low power operations
Major power savings may be accomplished by the appropriate programming of the
following registers in the CGU block.
Clock generation unit and power control
1.
12 MHz Oscillator Control register (OSCEN - address 0x8000 4C10):
When the bit 0 is set to 1, as it is after a reset, the 12MHz oscillator runs. The
application could clear this bit to save power if the whole CGU is driven by some
combination of the 32 KHz oscillator and the clock input pins.
2.
Fractional Divider Configuration registers:
If the application uses any of the Fractional Divider Configuration registers, then the
bits MADD and MSUB should be as large as possible in order to minimize power
consumption.
3.
Power control registers:
–
The application initialization code should write all zeroes to each of the unnamed
Power Control registers to minimize power consumption. The application
initialization code should also write all zeroes to each of the Power Control register
of the unused peripherals.
–
A 1 in the bit 3 (EXTEN_EN) of the Power Control register puts the corresponding
clock under control of a signal from the target module or sub module. This
functionality is typically used to reduce power consumption by disabling a clock
whenever it is not required. Set this bit only as indicated in
–
If the bit 2 (WAKE_EN) is 1, then the corresponding clock is enabled by a rising
edge on the Event Router’s Wakeup output, and disabled when the application
writes 3 to the CGUMode bits of the Power Mode register.
Applications that have floating inputs are recommended to switch to GPIO configuration to
save power. These pins should then be set as outputs.
There are also some registers in other blocks of the LPC288x that can also contribute to
power savings and they are listed below:
Processor cache and memory mapping
1.
Cache Settings register (CACHE_SETTINGS - address 0x8010 4004):
