NXP Semiconductors LPC2880, User Manual

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User manual Rev. 02 — 1 June 2007 68 of 362
NXP Semiconductors
UM10208
Chapter 7: LPC2800 CGU
3.12.2 Power status registers
The registers shown in Table 7–65 have the format shown in Table 7–66 .
Table 63. Power control register bit descriptions
Bit Symbol Description Reset
value
0 PCRUN A 0 in this bit disables the output clock of the spreading stage. 1
1 PCAUTO A 0 in this bit overrules bits 2 and 3, so that the clock output is
controlled only by the RUN bit and (if applicable) the selected
fractional divider. When this bit is 1, bits 2 and 3 have the effects
described below. 1
2 WAKE_EN A 0 in this bit makes this spreading stage independent of the wakeup
signal from the Event Router. If this bit is 1, this clock is enabled by a
rising edge on wakeup, and disabled when software writes 11 to the
Mode field of the Power Mode Control register (
Table 7–33 on
page 54 ).
1
3 EXTEN_EN A 1 in this bit puts this clock under control of a signal from the target
module or submodule. On the LPC288x this feature is used for
registers that have no dynamic operational aspects, and the control
signals are APB module select signals (PSEL). Set this bit only as
indicated in
Table 7–64 .
0
4 ENOUT_EN If this bit is 1, the spreading stage places its enable status on an
internal output named “enableout”. Set this bit only in AHB0PCR,
CPUPCR2, RAMPCR, and ROMPCR.
0
31:5 - Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined. -
Table 64. External enables validity by spreading stages
Set EXTEN_EN in: Do Not Set EXTEN_EN in:
IOCPCR MCIPCR0
CGUPCR UARTPCR0
SYSCPCR LCDPCR0
FLSHPCR2 WDTPCR
EVRTPCR I2CPCR
DMAPCR1
CPUPCR2
ADCPCR0