NXP Semiconductors LPC2880, User Manual

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User manual Rev. 02 — 1 June 2007 306 of 362
NXP Semiconductors
UM10208
Chapter 24: LPC2800 LCD
4.2 Control Register (LCDCTRL - 0x8010 3004)
Table 352. Control Register (LCDCTRL - 0x8010 3004)
Bit Symbol Description Reset
value
1 LCDPS 0 in this bit selects parallel mode, a 1 selects serial mode in which LD7
carries output data, LD6 is used for input data, and LD5 outputs the
serial clock. 0
2 LCDMI When PS is 0, a 0 in this bit selects 8080 mode, a 1 selects 6800
mode. 0
3 LCDW84 When PS is 0, a 0 in this bit selects 8-bit mode, a 1 selects 4-bit mode
in which only LD7:4 are used. 0
5:4 SCLKSEL When PS is 1, this field controls the timing of the serial clock on LD5:
00 produces a rising edge at the start of each bit cell, falling at 50%
01 produces a rising edge at 25% of the bit cell, falling at 75%
10 produces a falling edge at the start of each bit cell, rising at 50%
11 produces a falling edge at 25%, rising at 75% 11
7:6 SSAMPL When PS is 1, this field controls when the hardware samples LD6:
00: at the start of each bit cell
01: at 25% into each bit cell
10: halfway through each bit cell
11: at 75% into each bit cell. 11
8 LCDCBSY A 1 in this bit makes the hardware read a status register between data
transfers, and delay data transfer until a status bit allows it.
0
9 CBSENSE If CBUSY is 1, this bit determines which state of the bit selected by the
BUSYN field, the hardware will wait for before transferring data. If this
bit is 0, the hardware polls until the selected bit is 1/high, while if this
bit is 1, the hardware polls until the selected bit is 0/low.
0
12:10 LCDBSYN If CBUSY is 1, this field selects which signal among LD0:7 the
hardware checks before transferring data.
111
13 LRSSEL If CBUSY is 1, this bit determines which state of the LRS pin selects
the status register that contains the busy/ready indication. 0 means
LRS low selects the status register, 1 means LRS high selects the
status register. (The hardware uses the opposite state of LRS for the
data transfer.) 0
14 CSPOLAR 0 in this bit selects LCS as high-active, 1 selects low-active. 0
15 ERPOLAR A 1 in this bit inverts the LER output (inverted E in 6800 mode,
high-active RD in 8080 mode).
0
16 MSFIRST If PS is 1, a 1 in this bit selects bit 7 as the first to be sent for output,
and the first bit sampled to be placed in bit 7 when reading. If PS is 0
and W84 is 1, a 1 in this bit selects bits 7:4 as the first to be sent on
LD7:4 for output, and the first 4 bits sampled to be placed in bits 7:4
when reading. If PS is 0 and W84 is 0 this bit has no effect. 0