UM10208_2
© NXP B.V. 2007. All rights reserved.
User manual
Rev. 02 — 1 June 2007
290 of 362
NXP Semiconductors
UM10208
Chapter 23: LPC2800 SD/MMC
4.3.6 Data path
The card data bus width can be programmed using the clock control register. If the wide
bus mode is enabled, data is transferred at four bits per clock cycle over all four data
signals (MD3:0). If the wide bus mode is not enabled, only one bit per clock cycle is
transferred over MD0.
Depending on the transfer direction (send or receive), the Data Path State Machine
(DPSM) moves to the WAIT_S or WAIT_R state when it is enabled:
•
Send: The DPSM moves to the WAIT_S state. If there is data in the send FIFO, the
DPSM moves to the SEND state, and the data path subunit starts sending data to a
card.
•
Receive: The DPSM moves to the WAIT_R state and waits for a start bit. When it
receives a start bit, the DPSM moves to the RECEIVE state, and the data path subunit
starts receiving data from a card.
4.3.7 Data path state machine
The DPSM operates at MCICLK frequency. Data on the card bus signals is synchronous
to the rising edge of MCICLK. The DPSM has six states, as shown in
•
IDLE: The data path is inactive, and the MD3:0 outputs are in hi-Z. When the data
control register is written and the enable bit is set, the DPSM loads the data counter
with a new value and, depending on the data direction bit, moves to either the
WAIT_S or WAIT_R state.
WAIT_R: If the data counter equals zero, the DPSM moves to the IDLE state when
the receive FIFO is empty. If the data counter is not zero, the DPSM waits for a start
bit.
Fig 36. Data path state machine
IDLE
BUSY
SEND
WAIT_R
RECEIVE
WAIT_S
Reset
Disabled or
FIFO underrun or
end of data or
CRC fail
Disabled or
CRC fail or
timeout
Disabled or
end of data
Not busy
End of packet
Data ready
Enable
and send
Disabled or
Rx FIFO empty
or timeout or
start bit error
Enable and
not send
Disabled or
CRC fail
Start bit
End of packet
or end of data
or FIFO overrun
