NXP Semiconductors LPC24XX UM10237 User Manual Download Page 786

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UM10237_2

User manual

Rev. 02 — 19 December 2008

786 of 792

NXP Semiconductors

UM10237

Chapter 36: LPC24XX Supplementary information

7.4

SPI Clock Counter Register (S0SPCCR -
0xE002 000C). . . . . . . . . . . . . . . . . . . . . . . . 533

7.5

SPI Test Control Register (SPTCR -
0xE002 0010) . . . . . . . . . . . . . . . . . . . . . . . . 533

7.6

SPI Test Status Register (SPTSR - 0xE002 0014)
534

7.7

SPI Interrupt Register (S0SPINT - 0xE002 001C)
534

Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 534

Chapter 20: LPC24XX SSP interface SSP0/1

Basic configuration . . . . . . . . . . . . . . . . . . . . 536

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 536

Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . 537

Bus description . . . . . . . . . . . . . . . . . . . . . . . 537

5.1

Texas Instruments synchronous serial frame
format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537

5.2

SPI frame format . . . . . . . . . . . . . . . . . . . . . 538

5.2.1

Clock Polarity (CPOL) and Phase (CPHA) control
538

5.2.2

SPI format with CPOL=0,CPHA=0 . . . . . . . . 539

5.2.3

SPI format with CPOL=0,CPHA=1 . . . . . . . . 540

5.2.4

SPI format with CPOL = 1,CPHA = 0 . . . . . . 540

5.2.5

SPI format with CPOL = 1,CPHA = 1 . . . . . . 542

5.3

Semiconductor Microwire frame format . . . . 542

5.3.1

Setup and hold time requirements on CS with
respect to SK in Microwire mode . . . . . . . . . 544

Register description . . . . . . . . . . . . . . . . . . . 544

6.1

SSPn Control Register 0 (SSP0CR0 -
0xE006 8000, SSP1CR0 - 0xE003 0000) . . 545

6.2

SSPn Control Register 1 (SSP0CR1 -
0xE006 8004, SSP1CR1 - 0xE003 0004) . . 546

6.3

SSPn Data Register (SSP0DR - 0xE006 8008,
SSP1DR - 0xE003 0008) . . . . . . . . . . . . . . . 547

6.4

SSPn Status Register (SSP0SR - 0xE006 800C,
SSP1SR - 0xE003 000C). . . . . . . . . . . . . . . 548

6.5

SSPn Clock Prescale Register (SSP0CPSR -
0xE006 8010, SSP1CPSR - 0xE003 0010) . 548

6.6

SSPn Interrupt Mask Set/Clear Register
(SSP0IMSC - 0xE006 8014, SSP1IMSC -
0xE003 0014). . . . . . . . . . . . . . . . . . . . . . . . 548

6.7

SSPn Raw Interrupt Status Register (SSP0RIS -
0xE006 8018, SSP1RIS - 0xE003 0018) . . . 549

6.8

SSPn Masked Interrupt Status Register
(SSP0MIS - 0xE006 801C, SSP1MIS -
0xE003 001C) . . . . . . . . . . . . . . . . . . . . . . . 549

6.9

SSPn Interrupt Clear Register (SSP0ICR -
0xE006 8020, SSP1ICR - 0xE003 0020). . . 550

6.10

SSPn DMA Control Register (SSP0DMACR -
0xE006 8024, SSP1DMACR - 0xE003 0024). . .
550

Chapter 21: LPC24XX SD/MMC card interface

Basic configuration . . . . . . . . . . . . . . . . . . . . 551

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 551

Features of the MCI . . . . . . . . . . . . . . . . . . . . 551

SD/MMC card interface pin description . . . . 551

Functional overview . . . . . . . . . . . . . . . . . . . 552

5.1

Mutimedia card . . . . . . . . . . . . . . . . . . . . . . . 552

5.2

Secure digital memory card . . . . . . . . . . . . . 552

5.2.1

Secure digital memory card bus signals . . . . 553

5.3

MCI adapter . . . . . . . . . . . . . . . . . . . . . . . . . 553

5.3.1

Adapter register block. . . . . . . . . . . . . . . . . . 554

5.3.2

Control unit . . . . . . . . . . . . . . . . . . . . . . . . . . 554

5.3.3

Command path . . . . . . . . . . . . . . . . . . . . . . . 554

5.3.4

Command path state machine . . . . . . . . . . . 554

5.3.5

Command format . . . . . . . . . . . . . . . . . . . . . 556

5.3.6

Data path . . . . . . . . . . . . . . . . . . . . . . . . . . . 557

5.3.7

Data path state machine. . . . . . . . . . . . . . . . 557

5.3.8

Data counter . . . . . . . . . . . . . . . . . . . . . . . . . 559

5.3.9

Bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 560

5.3.10

CRC Token status. . . . . . . . . . . . . . . . . . . . . 560

5.3.11

Status flags . . . . . . . . . . . . . . . . . . . . . . . . . . 561

5.3.12

CRC generator . . . . . . . . . . . . . . . . . . . . . . . 561

5.3.13

Data FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . 561

5.3.14

Transmit FIFO. . . . . . . . . . . . . . . . . . . . . . . . 562

5.3.15

Receive FIFO . . . . . . . . . . . . . . . . . . . . . . . . 562

5.3.16

APB interfaces . . . . . . . . . . . . . . . . . . . . . . . 563

5.3.17

Interrupt logic . . . . . . . . . . . . . . . . . . . . . . . . 563

Register description . . . . . . . . . . . . . . . . . . . 563

6.1

Power Control Register (MCI Power -
0xE008 C000) . . . . . . . . . . . . . . . . . . . . . . . 564

6.2

Clock Control Register (MCIClock -
0xE008 C004) . . . . . . . . . . . . . . . . . . . . . . . 564

6.3

Argument Register (MCIArgument -
0xE008 C008) . . . . . . . . . . . . . . . . . . . . . . . 565

6.4

Command Register (MCICommand -
0xE008 C00C) . . . . . . . . . . . . . . . . . . . . . . . 565

6.5

Command Response Register
(MCIRespCommand - 0xE008 C010) . . . . . 566

6.6

Response Registers (MCIResponse0-3 -
0xE008 C014, E008 C018, E008 C01C and
E008 C020) . . . . . . . . . . . . . . . . . . . . . . . . . 566

6.7

Data Timer Register (MCIDataTimer -
0xE008 C024) . . . . . . . . . . . . . . . . . . . . . . . 567

6.8

Data Length Register (MCIDataLength -
0xE008 C028) . . . . . . . . . . . . . . . . . . . . . . . 567

6.9

Data Control Register (MCIDataCtrl -
0xE008 C02C) . . . . . . . . . . . . . . . . . . . . . . . 568

6.10

Data Counter Register (MCIDataCnt -
0xE008 C030) . . . . . . . . . . . . . . . . . . . . . . . 568

6.11

Status Register (MCIStatus - 0xE008 C034) 569

6.12

Clear Register (MCIClear - 0xE008 C038) . 570

6.13

Interrupt Mask Registers (MCIMask0 -
0xE008 C03C) . . . . . . . . . . . . . . . . . . . . . . . 570

Summary of Contents for LPC24XX UM10237

Page 1: ...cument information Info Content Keywords LPC2400 LPC2458 LPC2420 LPC2460 LPC2468 LPC2470 LPC2478 ARM ARM7 32 bit Single chip External memory interface USB 2 0 Device Host OTG Ethernet CAN I2S I2C SPI...

Page 2: ...resses please send an email to salesaddresses nxp com NXP Semiconductors UM10237 LPC24XX User manual Revision history Rev Date Description 02 20081219 LPC24XX user manual release Modifications Added p...

Page 3: ...S interface Supporting this collection of serial communications interfaces are the following feature components an on chip 4 MHz internal precision oscillator 98 kB of total RAM consisting of 64 kB of...

Page 4: ...nchronous static memory devices such as RAM ROM and Flash as well as dynamic memories such as Single Data Rate SDRAM Advanced Vectored Interrupt Controller VIC supporting up to 32 vectored interrupts...

Page 5: ...om the internal RC oscillator the RTC oscillator or the APB clock Standard ARM test debug interface for compatibility with existing tools Emulation trace module supports real time trace Single 3 3 V p...

Page 6: ...stic thin fine pitch ball grid array package 180 balls body 12 x 12 x 0 8 mm SOT570 2 Table 4 LPC2458 ordering options Type number Flash kB SRAM kB External bus Ethernet USB OTG OHC DEV 4 kB FIFO CAN...

Page 7: ...mber Package Name Description Version LPC2468FBD208 LQFP208 plastic low profile quad flat package 208 leads body 28 28 1 4 mm SOT459 1 LPC2468FET208 TFBGA208 plastic thin fine pitch ball grid array pa...

Page 8: ...PC2470 ordering options Type number Flash kB SRAM kB External bus Ethernet USB OTG OHC Device 4 kB FIFO CAN channels SD MMC GP DMA ADC channels DAC channels Temp range Local bus Ethernet buffer GP USB...

Page 9: ...complex instruction set computers This simplicity results in a high instruction throughput and impressive real time interrupt response from a small and cost effective processor core Pipeline techniqu...

Page 10: ...use This RAM may be used for code and or data storage and may be accessed as 8 bits 16 bits and 32 bits A 16 kB SRAM block serving as a buffer for the Ethernet controller and a 16 kB SRAM associated w...

Page 11: ...RNAL CONTROLLERS TEST DEBUG INTERFACE EMULATION TRACE MODULE trace signals AHB BRIDGE AHB BRIDGE ETHERNET MAC WITH DMA 16 kB SRAM MASTER PORT AHB TO AHB BRIDGE SLAVE PORT system clock SYSTEM FUNCTIONS...

Page 12: ...TERNAL SRAM CONTROLLER TEST DEBUG INTERFACE EMULATION TRACE MODULE trace signals AHB BRIDGE AHB BRIDGE ETHERNET MAC WITH DMA 1 16 kB SRAM 1 MASTER PORT AHB TO AHB BRIDGE SLAVE PORT system clock SYSTEM...

Page 13: ...RNAL CONTROLLERS TEST DEBUG INTERFACE EMULATION TRACE MODULE trace signals AHB BRIDGE AHB BRIDGE ETHERNET MAC WITH DMA 16 kB SRAM MASTER PORT AHB TO AHB BRIDGE SLAVE PORT system clock SYSTEM FUNCTIONS...

Page 14: ...OLLER TEST DEBUG INTERFACE EMULATION TRACE MODULE trace signals AHB BRIDGE AHB BRIDGE ETHERNET MAC WITH DMA 16 kB SRAM MASTER PORT AHB TO AHB BRIDGE SLAVE PORT system clock SYSTEM FUNCTIONS INTERNAL R...

Page 15: ...ONTROLLERS TEST DEBUG INTERFACE EMULATION TRACE MODULE trace signals AHB BRIDGE AHB BRIDGE ETHERNET MAC WITH DMA 16 kB SRAM MASTER PORT AHB TO AHB BRIDGE SLAVE PORT system clock SYSTEM FUNCTIONS INTER...

Page 16: ...32 bit Table 2 16 LPC2470 flashless yes 32 bit Table 2 15 LPC2478 512 kB yes 32 bit Table 2 16 Table 14 LPC2458 memory usage and details Address range General use Address range details and description...

Page 17: ...0000 0x81FF FFFF Static memory bank 1 0x8200 0000 0x82FF FFFF Static memory bank 2 0x8300 0000 0x83FF FFFF Static memory bank 3 Four dynamic memory banks 256 MB each 0xA000 0000 0xAFFF FFFF Dynamic m...

Page 18: ...Off Chip Memory Four static memory banks 16 MB each 0x8000 0000 0x80FF FFFF Static memory bank 0 0x8100 0000 0x81FF FFFF Static memory bank 1 0x8200 0000 0x82FF FFFF Static memory bank 2 0x8300 0000 0...

Page 19: ...ory map 0 0 GB 1 0 GB ON CHIP NON VOLATILE MEMORY OR RESERVED 0x0000 0000 RESERVED ADDRESS SPACE SPECIAL REGISTERS ON CHIP STATIC RAM RESERVED ADDRESS SPACE 0x4000 0000 0x3FFF 8000 0x3FFF FFFF 2 0 GB...

Page 20: ...h the AHB and APB peripheral areas are 2 megabyte spaces which are divided up into 128 peripherals Each peripheral space is 16 kilobytes in size This allows simplifying the address decoding for each p...

Page 21: ...n implication of this is that word and half word registers must be accessed all at once For example it is not possible to read or write the upper byte of a word register separately 1 LPC247x only Fig...

Page 22: ...001 4000 PWM0 6 0xE001 8000 PWM1 7 0xE001 C000 I2C0 8 0xE002 0000 SPI 9 0xE002 4000 RTC 10 0xE002 8000 GPIO 11 0xE002 C000 Pin Connect Block 12 0xE003 0000 SSP1 13 0xE003 4000 ADC 14 0xE003 8000 CAN A...

Page 23: ...0 0000 through 0x0000 001C as shown in Table 2 18 below a small portion of the Boot ROM and SRAM spaces need to be re mapped in order to allow alternative uses of interrupts in the different operating...

Page 24: ...ROM must contain branches to the actual interrupt handlers or to other instructions that accomplish the branch to the interrupt handlers There are three reasons this configuration was chosen 1 To give...

Page 25: ...s of data sets of 64 bytes each necessary for handling ARM exceptions interrupts For example whenever a Software Interrupt request is generated ARM core will always fetch 32 bit data residing on 0x000...

Page 26: ...appable areas for a LPC2400 part with flash 0 0 GB 0x8000 0000 0x4000 0000 0x3FFF FFFF 0x0000 0000 1 0 GB 2 0 GB 8 kB 2 0 GB ACTIVE INTERRUPT VECTORS FROM FLASH SRAM BOOT ROM OR EXT MEMORY BOOT FLASH...

Page 27: ...eral address or to the Special Register space located just below the SRAM at addresses 0x3FFF8000 through 0x3FFFFFFF Within the address space of an existing APB peripheral a data abort exception is no...

Page 28: ...on of each function UM10237 Chapter 3 LPC24XX System control Rev 02 19 December 2008 User manual Table 22 Pin summary Pin name Pin direction Pin description EINT0 Input External Interrupt Input 0 An a...

Page 29: ...AR and EXTMODE registers will set its interrupt flag in this register This asserts the corresponding interrupt request to the VIC which will cause an interrupt if interrupts from the pin are enabled W...

Page 30: ...01F C140 bit description Bit Symbol Description Reset value 0 EINT0 In level sensitive mode this bit is set if the EINT0 function is selected for its pin and the pin is in its active state In edge sen...

Page 31: ...In edge sensitive mode they select whether the pin is rising or falling edge sensitive Only pins that are selected for the EINT function see Section 9 5 5 and enabled in the VICIntEnable register Sec...

Page 32: ...reset logic is shown in Figure 3 10 Table 27 External Interrupt Polarity register EXTPOLAR address 0xE01F C14C bit description Bit Symbol Value Description Reset value 0 EXTPOLAR0 0 EINT0 is low acti...

Page 33: ...asserted The flash wakeup timer generates the 100 s flash start up time Once it times out the flash initialization sequence is started which takes about 250 cycles When it s done the MAM will be gran...

Page 34: ...startup boot code interaction 3 2 1 Reset Source Identification Register RSIR 0xE01F C180 This register contains one bit for each source of Reset Writing a 1 to any of these bits clears the correspon...

Page 35: ...to 2 5 V and continues to decline to the level at which POR is asserted nominally 1 V the BODR bit is cleared if the VDD 3V3 voltage rises continuously from below 1 V to a level above 2 6 V the BODR w...

Page 36: ...is not defined NA NA 3 MCIPWR Active Level 1 MCIPWR pin control R W 0 0 The MCIPWR pin is low 1 The MCIPWR pin is high 4 OSCRANGE Main oscillator range select R W 0 0 The frequency range of the main...

Page 37: ...the number of quanta before re arbiration occurs 0100 0000 Preemptive re arbitrate after 1 AHB quantum 0001 Preemptive re arbitrate after 2 AHB quanta 0010 Preemptive re arbitrate after 4 AHB quanta 0...

Page 38: ...sequence bit 0 0 LCD CPU GPDMA AHB1 USB Bit Symbol Description Priority value nnn Priority sequence 14 12 EP1 CPU 100 4 2 18 16 EP2 GPDMA 011 3 3 22 20 EP3 AHB1 010 2 4 26 24 EP4 USB 001 1 5 30 28 EP...

Page 39: ...e after 2 AHB quanta 0010 Preemptive re arbitrate after 4 AHB quanta 0011 Preemptive re arbitrate after 8 AHB quanta 0100 Preemptive re arbitrate after 16 AHB quanta 0101 Preemptive re arbitrate after...

Page 40: ...ularly executed event loop to sense the condition But when Brown Out Detection is enabled to bring the LPC2400 out of Power Down mode which is itself not a guaranteed operation see Section 4 3 4 6 Pow...

Page 41: ...the various clocks needed by the LPC2400 and options of clock source selection as well as power control and wakeup from reduced power modes Functions described in the following subsections include Os...

Page 42: ...NERATOR USB BLOCK ARM7 TDMI S ETHERNET BLOCK EMC LCD DMA FAST I O VIC EXTERNAL ETHERNET PHY 2 kB BATTERY RAM USB CLOCK DIVIDER system clock select CLKSRCSEL WDT clock select WDTCLKSEL RTC clock select...

Page 43: ...rces 2 2 Main oscillator The main oscillator can be used as the clock source for the CPU with or without using the PLL The main oscillator operates at frequencies of 1 MHz to 24 MHz This frequency can...

Page 44: ...39 Recommended values for CX1 X2 in oscillation mode crystal and external components parameters low frequency mode OSCRANGE 0 see Table 3 29 Fundamental oscillation frequency FOSC Crystal load capaci...

Page 45: ...ces available are the main oscillator the RTC oscillator and the Internal RC IRC oscillator The clock source selection can only be changed safely when the PLL is not connected For a detailed descripti...

Page 46: ...der output through the use of a Current Controlled Oscillator CCO by a value M in the range of 1 through 32768 The resulting frequency must be in the range of 275 MHz to 550 MHz The multiplier works b...

Page 47: ...ips When there is no valid code determined by the checksum word in the user flash or the ISP enable pin P2 10 is pulled low on startup the ISP mode will be entered and the boot code will setup the PLL...

Page 48: ...quence has taken place R W 0 0xE01F C080 PLLCFG PLL Configuration Register Holding register for updating PLL configuration values Values written to this register do not take effect until a valid PLL f...

Page 49: ...s The value stored here is M 1 Supported values for M are 6 through 512 and those listed in Table 4 46 Note Not all values of M are needed and therefore some are not supported by hardware For details...

Page 50: ...7 9980 9155 2 299 9910 9613 2 314 9988 10254 2 336 0031 10376 2 340 0008 10986 2 359 9892 11719 2 384 0082 12085 2 396 0013 12207 2 399 9990 12817 2 419 9875 12817 3 279 9916 13184 2 432 0133 13184 3...

Page 51: ...a 32 kHz oscillator Multiplier M Pre divide N FCCO Table 47 PLL Status register PLLSTAT address 0xE01F C088 bit description Bit Symbol Description Reset value 14 0 MSEL Read back for the PLL Multipli...

Page 52: ...rrupts must be disabled for the duration of the PLL feed operation If either of the feed values is incorrect or one of the previously mentioned conditions is not met any changes to the PLLCON or PLLCF...

Page 53: ...nal M values have been selected for supporting baud rate generation CAN USB operation and attaining even MHz frequencies These values are shown in Table 4 51 Table 50 PLL frequency parameter Parameter...

Page 54: ...e a value for the PLL input frequency FIN This can be a clock obtained from the main oscillator the RTC oscillator or the on chip RC oscillator For USB support the main oscillator should be used 4 Cal...

Page 55: ...not be used in the application The desired CPU rate 72 MHz The 32 768 kHz RTC clock source will be used as the system clock source Calculations M FCCO N 2 FIN The smallest frequency for FCCO that can...

Page 56: ...Clock Divider setting to speed up operation without the PLL if desired 4 Write to the Clock Source Selection Control register to change the clock source 5 Write to the PLLCFG and make it effective wi...

Page 57: ...ided in order to bring the USB clock frequency to 48 MHz with a 50 duty cycle A 4 bit divider allows obtaining the correct USB clock from any even multiple of 48 MHz i e any mutliple of 96 MHz within...

Page 58: ...ion for TIMER0 00 5 4 PCLK_TIMER1 Peripheral clock selection for TIMER1 00 7 6 PCLK_UART0 Peripheral clock selection for UART0 00 9 8 PCLK_UART1 Peripheral clock selection for UART1 00 11 10 PCLK_PWM0...

Page 59: ...referred to as the Battery RAM This feature is described in more detail later in this chapter under the heading Power Domains and in the Real Time Clock and Battery RAM chapter 3 4 1 Idle mode When I...

Page 60: ...counting and the code execution and peripherals activities will resume after the timer expires 4 cycles If the main external oscillator was used the 12 bit main oscillator timer starts counting and th...

Page 61: ...s Register This register contains control bits that enable and disable individual peripheral functions allowing elimination of power consumption by peripherals that are not needed R W 0xE01F C0C4 Tabl...

Page 62: ...s also necessary to clear the corresponding interrupt flag see Section 3 3 1 2 External Interrupt flag register EXTINT 0xE01F C140 4 BORD Brown Out Reset Disable When BORD is 1 the second stage of low...

Page 63: ...elationship of USB to Power down Mode and wakeup see the relevant USB chapter s 0 6 CANWAKE When one activity of the CAN bus will wake up the processor from Power down mode Any change of state on the...

Page 64: ...ripherals register PCONP address 0xE01F C0C4 bit description Bit Symbol Description Reset value 0 Unused always 0 0 1 PCTIM0 Timer Counter 0 power clock control bit 1 2 PCTIM1 Timer Counter 1 power cl...

Page 65: ...d and power removed the RTC can supply an alarm output that may be used by external hardware to restore chip power and resume operation Details may be found in Section 26 8 Note The RTC and the batter...

Page 66: ...ower down mode some time is required for the oscillator to produce a signal of sufficient amplitude to drive the clock logic The amount of time depends on many factors including the rate of VDD 3V3 ra...

Page 67: ...Data bus width memory transaction size Pins SDRAM configuration registers Static memory configuration registers External memory connection LPC2458 8 bit 16 bit A 19 0 D 15 0 OE WE BLS 1 0 CS 1 0 DYCS...

Page 68: ...ith or without asynchronous page mode Low transaction latency Read and write buffers to reduce latency and to improve performance 8 bit 16 bit and 32 bit wide static memory support 16 bit and 32 bit w...

Page 69: ...slave register interface block enables the registers of the EMC to be programmed This module also contains most of the registers and performs the majority of the register address decoding To eliminat...

Page 70: ...provides the interface to the pads The pad interface uses feedback clocks FBCLKIN 3 0 to resynchronize SDRAM read data from the off chip to on chip domains 5 4 Data buffers The AHB interface reads an...

Page 71: ...from the buffer rather than memory reducing transaction latency Convert all read transactions into quadword bursts on the external memory interface This enhances transfer efficiency for dynamic memory...

Page 72: ...is powered down and no longer refreshed All data in the memory is lost 6 2 Low power SDRAM partial array refresh The EMC supports JEDEC low power SDRAM partial array refresh Partial array refresh can...

Page 73: ...ned through a warm reset 9 Pin description Table 5 66 shows the interface and control signal pins for the EMC Table 66 Pad interface and control signal descriptions Name Type Value on POR reset Value...

Page 74: ...efresh operation 0x0 R W 0xFFE0 8028 EMCDynamic ReadConfig Configures the dynamic memory read strategy 0x0 R W 0xFFE0 8030 EMCDynamicRP Selects the precharge command period 0x0F R W 0xFFE0 8034 EMCDyn...

Page 75: ...r static chip select 1 0x0 R W 0xFFE0 8224 EMCStatic WaitWen1 Selects the delay from chip select 1 to write enable 0x0 R W 0xFFE0 8228 EMCStatic WaitOen1 Selects the delay from chip select 1 or addres...

Page 76: ...R W 0xFFE0 8274 EMCStatic WaitWr3 Selects the delay from chip select 3 to a write access 0x1F R W 0xFFE0 8278 EMCStatic WaitTurn3 Selects the number of bus turnaround cycles for chip select 3 0xF R W...

Page 77: ...MC is in idle state 1 31 3 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined NA Table 68 EMC Control register EMCControl address 0xFFE0 80...

Page 78: ...set Value 0 Endian mode 0 0 Little endian mode POR reset value 1 Big endian mode On power on reset the value of the endian bit is 0 All data must be flushed in the EMC before switching between little...

Page 79: ...re control Writing 0 to this bit returns the EMC to normal mode The self refresh acknowledge bit in the EMCStatus register must be polled to discover the current operating mode of the EMC 2 4 3 Reserv...

Page 80: ...106 16 50 or 0x32 If auto refresh through warm reset is requested by setting the EMC_Reset_Disable bit the timing of auto refresh must be adjusted to allow a sufficient refresh rate when the clock rat...

Page 81: ...namicReadConfig register 10 7 Dynamic Memory Percentage Command Period register EMCDynamictRP 0xFFE0 8030 The EMCDynamicTRP register enables you to program the precharge command period tRP This regist...

Page 82: ...n there are no current or outstanding transactions This can be ensured by waiting until the EMC is idle and then entering low power or disabled mode This value is normally found in SDRAM data sheets a...

Page 83: ...odified during system initialization or when there are no current or outstanding transactions This can be ensured by waiting until the EMC is idle and then entering low power or disabled mode This val...

Page 84: ...r is modified during system initialization or when there are no current or outstanding transactions This can be ensured by waiting until the EMC is idle and then entering low power or disabled mode Th...

Page 85: ...odified during system initialization or when there are no current or outstanding transactions This can be ensured by waiting until the EMC is idle and then entering low power or disabled mode This val...

Page 86: ...fied during system initialization or when there are no current or outstanding transactions This can be ensured by waiting until the EMC is idle and then entering low power or disabled mode This value...

Page 87: ...nfig0 3 registers enable you to program the configuration information for the relevant dynamic memory chip select These registers are normally only modified during system initialization These register...

Page 88: ...erved bit is not defined NA 12 7 Address mapping AM See Table 5 87 0 0 000000 reset value 1 13 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not d...

Page 89: ...2 banks row length 11 column length 8 1 0 001 00 64 MB 8Mx8 4 banks row length 12 column length 9 1 0 001 01 64 MB 4Mx16 4 banks row length 12 column length 8 1 0 001 10 64 MB 2Mx32 4 banks row length...

Page 90: ...rrent or outstanding transactions This can be ensured by waiting until the EMC is idle and then entering low power or disabled mode These registers are accessed with one wait state Note The values pro...

Page 91: ...le 89 Static Memory Configuration registers EMCStaticConfig0 3 address 0xFFE0 8200 0xFFE0 8220 0xFFE0 8240 0xFFE0 8260 bit description Bit Symbol Value Description Reset Value 1 0 Memory width MW 00 8...

Page 92: ...UBn and LBn upper byte and lower byte signals in the static memory In this case a write to a particular byte must assert the appropriate UBn or LBn signal LOW For reads all the UB and LB signals must...

Page 93: ...outstanding transactions This can be ensured by waiting until the EMC is idle and then entering low power or disabled mode It is not used if the extended wait bit is enabled in the EMCStaticConfig0 3...

Page 94: ...er These registers are accessed with one wait state Table 5 94 shows the bit assignments for the EMCStaticWaitWr0 3 registers Table 92 Static Memory Read Delay registers EMCStaticWaitRd0 3 address 0xF...

Page 95: ...be 32 bits wide address lines A0 and A1 can be used as non address lines If a memory bank is configured to 16 bits wide A0 is not required However 8 bit wide memory banks do require all address lines...

Page 96: ...y for flashless devices refer to Section 8 6 on how to connect the EMC The memory bank width for memory banks 1 and 2 is determined by the setting of the two BOOT1 0 pins 11 1 32 bit wide memory bank...

Page 97: ...6 32 bit bank external memory interfaces bits MW 10 OE CS WE CE OE WE B3 B2 B1 B0 IO 31 0 A a_m 0 D 31 0 BLS 2 A a_b 2 BLS 3 BLS 0 BLS 1 a 16 bit wide memory bank interfaced to two 8 bit memory chips...

Page 98: ...Rev 02 19 December 2008 98 of 792 NXP Semiconductors UM10237 Chapter 5 LPC24XX External Memory Controller EMC 11 3 8 bit wide memory bank connection Fig 18 8 bit bank external memory interface bits M...

Page 99: ...guration diagram nCE nOE Q 31 0 A 20 0 nCE nOE IO 15 0 A 15 0 nWE nUB nLB nCE nOE IO 15 0 A 15 0 nWE nUB nLB nCE nOE IO 7 0 A 16 0 nWE nCE nOE IO 7 0 A 16 0 nWE nCE nOE IO 7 0 A 16 0 nWE nCE nOE IO 7...

Page 100: ...e core presents a different address from the one from which the prefetch has been made the prefetched line is discarded The prefetch and Branch Trail buffers each include four 32 bit ARM instructions...

Page 101: ...ry Acceleration Module blocks The Memory Accelerator Module is divided into several functional blocks A Flash Address Latch and an incrementor function to form prefetch addresses A 128 bit prefetch bu...

Page 102: ...This is accomplished by asserting the ARM7TDMI S local bus signal CLKEN Under some conditions this delay could result in a Watchdog time out The user will need to be aware of this possibility and take...

Page 103: ...s available but mimics the timing of a Flash read operation This saves power while resulting in the same execution timing The MAM can truly be turned off by setting the fetch timing value in MAMTIM to...

Page 104: ...tees synchronization of the MAM to CPU operation 7 2 MAM Timing Register MAMTIM 0xE01F C004 The MAM Timing register determines how many CCLK cycles are used to access the Flash memory This allows tuni...

Page 105: ...rations 07 000 0 Reserved 001 1 MAM fetch cycles are 1 processor clock CCLK in duration 010 2 MAM fetch cycles are 2 CCLKs in duration 011 3 MAM fetch cycles are 3 CCLKs in duration 100 4 MAM fetch cy...

Page 106: ...r a system clock between 20 MHz and 40 MHz flash access time is suggested to be 2 CCLKs while in systems with a system clock faster than 40 MHz 3 CCLKs are proposed For system clocks of 60 MHz and abo...

Page 107: ...8 107 of 792 NXP Semiconductors UM10237 Chapter 6 LPC24XX Memory Accelerator Module MAM Table 101 Suggestions for MAM timing selection system clock Number of MAM fetch cycles in MAMTIM see Table 6 100...

Page 108: ...Rs the requests to produce the FIQ signal to the ARM processor The fastest possible FIQ latency is achieved when only one request is classified as FIQ because then the FIQ service routine can simply s...

Page 109: ...register allows software to clear one or more bits in the Software Interrupt register WO 0xFFFF F01C VICProtection Protection enable register This register allows limiting access to the VIC registers...

Page 110: ...ctPriority4 Vector priority 4 register R W 0xF 0xFFFF F210 VICVectPriority5 Vector priority 5 register R W 0xF 0xFFFF F214 VICVectPriority6 Vector priority 6 register R W 0xF 0xFFFF F218 VICVectPriori...

Page 111: ...ng or classification VICVectPriority26 Vector priority 26 register R W 0xF 0xFFFF F268 VICVectPriority27 Vector priority 27 register R W 0xF 0xFFFF F26C VICVectPriority28 Vector priority 28 register R...

Page 112: ...value 31 0 See Table 7 117 Interrupt sources bit allocation table 0 Neither the hardware nor software interrupt request with this bit number are asserted 1 The hardware or software interrupt request w...

Page 113: ...the addresses of the Interrupt Service routines ISRs for the 32 vectored IRQ slots Table 108 Interrupt Select register VICIntSelect address 0xFFFF F00C bit description Bit Symbol Value Description Re...

Page 114: ...Vector Address registers 0 31 VICVectAddr0 31 addresses 0xFFFF F100 to 0xFFFF F17C bit description Bit Symbol Description Reset value 31 0 VICVectAddr The VIC provides the contents of one of these re...

Page 115: ...vel is masked 0xFFFF 1 Interrupt priority level is not masked 31 16 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined NA Table 115 Protect...

Page 116: ...RTC Counter Increment RTCCIF Alarm RTCALF Subsecond Int RTCSSF 13 0x0000 2000 System Control External Interrupts External Interrupt 0 EINT0 14 0x0000 4000 External Interrupt 1 EINT1 15 0x0000 8000 Ext...

Page 117: ...Line Status RLS Transmit Holding Register Empty THRE Rx Data Available RDA Character Time out Indicator CTI End of Auto Baud ABEO Auto Baud Time Out ABTO 28 0x1000 0000 UART 3 Rx Line Status RLS Trans...

Page 118: ...QStatus 31 0 FIQ interrupt request masking and selection VectPriority0 3 0 PRIORITY MASKING LOGIC VectAddr0 31 0 IRQStatus 0 SWPriorityMask 0 HWPriorityMask 0 VectIRQ0 Vect Addr0 31 0 D Q D Q vectored...

Page 119: ...ation Rev 02 19 December 2008 User manual Table 118 LPC2400 pin configurations overview Part Pins Pin packages Pin allocation Pin description Boot control LQFP208 TFBGA180 208 TFBGA180 208 LPC2458 180...

Page 120: ...kage LPC2400FET208 Transparent top view ball A1 index area U T R P N M K H L J G F E D C A B 2 4 6 8 10 12 13 14 15 17 16 1 3 5 7 9 11 Table 119 LPC2458 pin allocation table Pin Symbol Pin Symbol Pin...

Page 121: ...TCK 3 P3 4 D4 4 TRST 5 P0 2 TXD0 6 P3 0 D0 7 P1 9 ENET_RXD0 8 P1 14 ENET_RX_ER 9 P4 25 WE 10 P4 28 BLS2 MAT2 0 TXD3 11 P0 6 I2SRX_SDA SSEL1 MAT2 0 12 P2 0 PWM1 1 TXD1 TRACECLK 13 VSSIO 14 P1 13 ENET_R...

Page 122: ...AT0 1 PWM1 3 8 VDD 3V3 9 P4 3 A3 10 P4 6 A6 11 P0 21 RI1 MCIPWR RD1 12 P4 7 A7 13 P4 26 BLS0 14 P0 20 DTR1 MCICMD SCL1 15 16 Row L 1 P2 29 DQMOUT1 2 XTAL1 3 P0 27 SDA0 4 VDD 3V3 5 P1 18 USB_UP_LED1 PW...

Page 123: ...nnect block P0 0 RD1 TXD3 SDA1 M10 1 I O P0 0 General purpose digital input output pin I RD1 CAN1 receiver input O TXD3 Transmitter output for UART3 I O SDA1 I2C1 data input output this is not an open...

Page 124: ...l purpose digital input output pin I O I2STX_SDA Transmit data It is driven by the transmitter and read by the receiver Corresponds to the signal SD in the I2S bus specification I O MOSI1 Master Out S...

Page 125: ...Out for SSP0 I O MISO Master In Slave Out for SPI P0 18 DCD1 MOSI0 MOSI J13 1 I O P0 18 General purpose digital input output pin I DCD1 Data Carrier Detect input for UART1 I O MOSI0 Master Out Slave...

Page 126: ...t for UART3 P0 27 SDA0 L3 4 I O P0 27 General purpose digital input output pin Output is open drain I O SDA0 I2C0 data input output Open drain output for I2C bus compliance P0 28 SCL0 M1 4 I O P0 28 G...

Page 127: ...8 ENET_CRS_DV ENET_CRS B6 1 I O P1 8 General purpose digital input output pin I ENET_CRS_DV ENET_CRS Ethernet Carrier Sense Data Valid RMII interface Ethernet Carrier Sense MII interface P1 9 ENET_RXD...

Page 128: ...O PWM1 2 Pulse Width Modulator 1 channel 2 output I O SCK0 Serial clock for SSP0 P1 21 USB_TX_DM1 PWM1 3 SSEL0 N6 1 I O P1 21 General purpose digital input output pin O USB_TX_DM1 D transmit data for...

Page 129: ...General purpose digital input output pin I USB_PWRD2 Power Status for USB port 2 I VBUS Monitors the presence of USB bus power Note This signal must be HIGH for USB reset to occur I AD0 4 A D converte...

Page 130: ...General purpose digital input output pin I RD2 CAN2 receiver input O RTS1 Request to Send output for UART1 O TRACEPKT2 Trace Packet bit 2 P2 8 TD2 TXD2 TRACEPKT3 G14 1 I O P2 8 General purpose digital...

Page 131: ...OUT1 SDRAM clock 1 P2 20 DYCS0 P6 1 I O P2 20 General purpose digital input output pin O DYCS0 SDRAM chip select 0 P2 21 DYCS1 N8 1 I O P2 21 General purpose digital input output pin O DYCS1 SDRAM chi...

Page 132: ...P3 13 D13 C1 1 I O P3 13 General purpose digital input output pin I O D13 External memory data line 13 P3 14 D14 F1 1 I O P3 14 General purpose digital input output pin I O D14 External memory data l...

Page 133: ...address line 8 P4 9 A9 H12 1 I O P4 9 General purpose digital input output pin I O A9 External memory address line 9 P4 10 A10 G12 1 I O P4 10 General purpose digital input output pin I O A10 Externa...

Page 134: ...ARM RTC controlled output This is a 1 8 V pin It goes HIGH when a RTC alarm is generated USB_D 2 N2 I O USB_D 2 USB port 2 bidirectional D line DBGEN E5 1 I DBGEN JTAG interface control signal Also us...

Page 135: ...d provides special analog functionality 9 Pad provides special analog functionality 10 Pad provides special analog functionality 11 Pad provides special analog functionality 12 Pad provides special an...

Page 136: ...P3 0 D0 5 P1 1 ENET_TXD1 6 VSSIO 7 P4 30 CS0 8 P4 24 OE 9 P4 25 WE 10 P4 29 BLS3 MAT2 1 RXD3 11 P1 6 ENET_TX_CLK MCIDAT0 PWM0 4 12 P0 4 I2SRX_CLK RD2 CAP2 0 13 VDD 3V3 14 P3 19 D19 PWM0 4 DCD1 15 P4 1...

Page 137: ...3 31 D31 MAT1 2 4 NC 14 P0 16 RXD1 SSEL0 SSEL 15 P4 23 A23 RXD2 MOSI1 16 P0 15 TXD1 SCK0 SCK 17 P4 8 A8 Row K 1 VREF 2 RTCX1 3 RSTOUT 4 VSSCORE 14 P4 22 A22 TXD2 MISO1 15 P0 18 DCD1 MOSI0 MOSI 16 VDD...

Page 138: ...D26 MAT0 1 PWM1 3 4 P2 26 CKEOUT2 MAT3 0 MISO0 5 VSSIO 6 P3 23 D23 CAP0 0 PCAP1 0 7 P0 14 USB_HSTEN2 USB_CONNECT2 SSEL1 8 P2 20 DYCS0 9 P1 24 USB_RX_DM1 PWM1 5 MOSI0 10 P1 25 USB_LS1 USB_HSTEN1 MAT1 1...

Page 139: ...received by the slave Corresponds to the signal SCK in the I2S bus specification I RD2 CAN2 receiver input LPC2460 only I CAP2 0 Capture input for Timer 2 channel 0 P0 5 I2SRX_WS TD2 CAP2 1 166 1 C12...

Page 140: ...put 6 P0 13 USB_UP_LED2 MOSI1 AD0 7 45 2 R2 2 I O P0 13 General purpose digital input output pin O USB_UP_LED2 USB port 2 GoodLink LED indicator It is LOW when device is configured non control endpoin...

Page 141: ...nput output pin O RTS1 Request to Send output for UART1 I O MCIDAT0 Data line 0 for SD MMC interface O TD1 CAN1 transmitter output LPC2460 only P0 23 AD0 0 I2SRX_CLK CAP3 0 18 2 H1 2 I O P0 23 General...

Page 142: ...194 1 B5 1 I O P1 1 General purpose digital input output pin O ENET_TXD1 Ethernet transmit data 1 RMII MII interface LPC2460 only P1 2 ENET_TXD2 MCICLK PWM0 1 185 1 D9 1 I O P1 2 General purpose digit...

Page 143: ...rpose digital input output pin I ENET_RXD3 Ethernet Receive Data MII interface LPC2460 only I O MCIDAT3 Data line 3 for SD MMC interface I PCAP0 0 Capture input for PWM0 channel 0 P1 13 ENET_RX_DV 147...

Page 144: ..._DP1 D receive data for USB port 1 OTG transceiver O PWM1 4 Pulse Width Modulator 1 channel 4 output I O MISO0 Master In Slave Out for SSP0 P1 24 USB_RX_DM1 PWM1 5 MOSI0 78 1 T9 1 I O P1 24 General pu...

Page 145: ...General purpose digital input output pin O PWM1 1 Pulse Width Modulator 1 channel 1 output O TXD1 Transmitter output for UART1 O TRACECLK Trace Clock P2 1 PWM1 2 RXD1 PIPESTAT0 152 1 E14 1 I O P2 1 Ge...

Page 146: ...W forces on chip bootloader to take over control of the part after a reset I EINT0 External interrupt 0 input P2 11 EINT1 MCIDAT1 I2STX_CLK 108 6 T17 6 I O P2 11 General purpose digital input output p...

Page 147: ...ital input output pin O DYCS2 SDRAM chip select 2 I CAP3 0 Capture input for Timer 3 channel 0 I O SCK0 Serial clock for SSP0 P2 23 DYCS3 CAP3 1 SSEL0 64 1 U5 1 I O P2 23 General purpose digital input...

Page 148: ...E4 1 I O P3 3 General purpose digital input output pin I O D3 External memory data line 3 P3 4 D4 13 1 F2 1 I O P3 4 General purpose digital input output pin I O D4 External memory data line 4 P3 5 D5...

Page 149: ...ory data line 18 O PWM0 3 Pulse Width Modulator 0 output 3 I CTS1 Clear to Send input for UART1 P3 19 D19 PWM0 4 DCD1 161 1 B14 1 I O P3 19 General purpose digital input output pin I O D19 External me...

Page 150: ...ternal memory data line 28 I CAP1 1 Capture input for Timer 1 channel 1 O PWM1 5 Pulse Width Modulator 1 output 5 P3 29 D29 MAT1 0 PWM1 6 11 1 F3 1 I O P3 29 General purpose digital input output pin I...

Page 151: ...digital input output pin I O A11 External memory address line 11 P4 12 A12 149 1 C16 1 I O P4 12 General purpose digital input output pin I O A12 External memory address line 12 P4 13 A13 155 1 B16 1...

Page 152: ...P4 27 BLS1 139 1 G15 1 I O P4 27 General purpose digital input output pin O BLS1 LOW active Byte Lane select signal 1 P4 28 BLS2 MAT2 0 TXD3 170 1 C11 1 I O P4 28 General purpose digital input output...

Page 153: ...SSIO 33 63 77 93 114 133 148 169 189 200 8 L3 T5 R9 P12 N16 H14 E15 A12 B6 A2 8 I ground 0 V reference for the digital I O pins VSSCORE 32 84 172 8 K4 P10 D12 8 I ground 0 V reference for the core VSS...

Page 154: ...ls and hysteresis 7 5 V tolerant pad with 20 ns glitch filter providing digital I O function with TTL levels and hysteresis 8 Pad provides special analog functionality 5 LPC2470 78 pinning information...

Page 155: ...RXD1 PIPESTAT0 LCDLE 15 VSSIO 16 P2 3 PWM1 4 DCD1 PIPESTAT2 LCDFP 17 P2 6 PCAP1 0 RI1 TRACEPKT1 LCDVD 0 LCDVD 4 Row F 1 P0 25 AD0 2 I2SRX_SDA TXD3 2 P3 4 D4 3 P3 29 D29 MAT1 0 PWM1 6 4 DBGEN 14 P4 11...

Page 156: ...2 27 CKEOUT3 MAT3 1 MOSI0 4 P2 28 DQMOUT0 5 P2 24 CKEOUT0 6 VDD 3V3 7 P1 18 USB_UP_LED1 PWM1 1 CAP1 0 8 VDD 3V3 9 P1 23 USB_RX_DP1 LCDVD 9 LCDVD 13 PWM1 4 MISO0 10 VSSCORE 11 VDD DCDC 3V3 12 VSSIO 13...

Page 157: ...15 LCDVD 23 PCAP1 1 MAT0 1 15 P0 0 RD1 TXD3 SDA1 16 P4 3 A3 17 P4 16 A16 Table 123 LPC2470 78 pin allocation table continued Pin Symbol Pin Symbol Pin Symbol Pin Symbol Table 124 LPC2470 78 pin descri...

Page 158: ...2S bus specification 15 O LCDVD 8 LCD data 15 I O SSEL1 Slave Select for SSP1 O MAT2 0 Match output for Timer 2 channel 0 P0 7 I2STX_CLK LCDVD 9 SCK1 MAT2 1 162 1 C13 1 I O P0 7 General purpose digita...

Page 159: ...during global suspend I O MOSI1 Master Out Slave In for SSP1 I AD0 7 A D converter 0 input 7 P0 14 USB_HSTEN2 USB_CONNECT2 SSEL1 69 1 T7 1 I O P0 14 General purpose digital input output pin O USB_HSTE...

Page 160: ...nput 0 I O I2SRX_CLK Receive Clock It is driven by the master and received by the slave Corresponds to the signal SCK in the I2S bus specification I CAP3 0 Capture input for Timer 3 channel 0 P0 24 AD...

Page 161: ...net transmit data 3 MII interface I O MCICMD Command line for SD MMC interface O PWM0 2 Pulse Width Modulator 0 output 2 P1 4 ENET_TX_EN 192 1 A5 1 I O P1 4 General purpose digital input output pin O...

Page 162: ...ENET_MDIO 178 1 A9 1 I O P1 17 General purpose digital input output pin I O ENET_MDIO Ethernet MIIM data input and output P1 18 USB_UP_LED1 PWM1 1 CAP1 0 66 1 P7 1 I O P1 18 General purpose digital in...

Page 163: ..._LS1 LCDVD 11 LCDVD 15 USB_HSTEN1 MAT1 1 80 1 T10 1 I O P1 25 General purpose digital input output pin O USB_LS1 Low Speed status for USB port 1 OTG transceiver 16 O LCDVD 11 LCDVD 15 LCD data 16 O US...

Page 164: ...General purpose digital input output pin I USB_PWRD2 Power Status for USB port 2 I VBUS Monitors the presence of USB bus power Note This signal must be HIGH for USB reset to occur I AD0 4 A D convert...

Page 165: ...t for UART1 O PIPESTAT2 Pipeline status bit 2 17 O LCDFP Frame pulse STN Vertical synchronization pulse TFT 17 P2 4 PWM1 5 DSR1 TRACESYNC LCDENAB LCDM 142 1 D17 1 I O P2 4 General purpose digital inpu...

Page 166: ...y the master and received by the slave Corresponds to the signal SCK in the I2S bus specification P2 12 EINT2 LCDVD 4 LCDVD 3 LCDVD 8 LCDVD 18 MCIDAT2 I2STX_WS 106 6 N14 6 I O P2 12 General purpose di...

Page 167: ...I CAP3 1 Capture input for Timer 3 channel 1 I O SSEL0 Slave Select for SSP0 P2 24 CKEOUT0 53 1 P5 1 I O P2 24 General purpose digital input output pin O CKEOUT0 SDRAM clock enable 0 P2 25 CKEOUT1 54...

Page 168: ...l purpose digital input output pin I O D4 External memory data line 4 P3 5 D5 17 1 G1 1 I O P3 5 General purpose digital input output pin I O D5 External memory data line 5 P3 6 D6 23 1 J1 1 I O P3 6...

Page 169: ...mory data line 18 O PWM0 3 Pulse Width Modulator 0 output 3 I CTS1 Clear to Send input for UART1 P3 19 D19 PWM0 4 DCD1 161 1 B14 1 I O P3 19 General purpose digital input output pin I O D19 External m...

Page 170: ...xternal memory data line 28 I CAP1 1 Capture input for Timer 1 channel 1 O PWM1 5 Pulse Width Modulator 1 output 5 P3 29 D29 MAT1 0 PWM1 6 11 1 F3 1 I O P3 29 General purpose digital input output pin...

Page 171: ...e digital input output pin I O A11 External memory address line 11 P4 12 A12 149 1 C16 1 I O P4 12 General purpose digital input output pin I O A12 External memory address line 12 P4 13 A13 155 1 B16...

Page 172: ...39 1 G15 1 I O P4 27 General purpose digital input output pin O BLS1 LOW active Byte Lane select signal 1 P4 28 BLS2 MAT2 0 LCDVD 6 LCDVD 10 LCDVD 2 TXD3 170 1 C11 1 I O P4 28 General purpose digital...

Page 173: ...VSSIO 33 63 77 93 114 133 148 169 189 200 9 L3 T5 R9 P12 N16 H14 E15 A12 B6 A2 9 I ground 0 V reference for the digital IO pins VSSCORE 32 84 172 9 K4 P10 D12 9 I ground 0 V reference for the core VSS...

Page 174: ...Pad provides special analog functionality 13 Pad provides special analog functionality 14 Pad provides special analog functionality 15 Either the I2S function or the LCD function is selectable 16 Eith...

Page 175: ...Pin configuration the address mirror bit is set in the EMCControl register during POR see Table 5 68 Therefore the user code residing in the external boot memory must be linked to execute from addres...

Page 176: ...Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined Selecting a single function on a port pin completely excludes all other functions otherw...

Page 177: ...5 5 Register description The Pin Control Module contains 12 registers as shown in Table 9 129 below Remark The LCD pins in the PINSEL registers are available on the LPC247x only Table 127 Pin function...

Page 178: ...00 0000 0xE002 C018 PINSEL7 Pin function select register 7 R W 0x0000 0000 0xE002 C01C PINSEL8 Pin function select register 8 R W 0x0000 0000 0xE002 C020 PINSEL9 Pin function select register 9 R W 0x0...

Page 179: ...D2 SCL2 MAT3 1 00 25 24 P0 12 GPIO Port 0 12 USB_PPWR2 MISO1 AD0 6 00 27 26 P0 13 GPIO Port 0 13 USB_UP_LED2 MOSI1 AD0 7 00 29 28 P0 14 GPIO Port 0 14 USB_HSTEN2 USB_CONN ECT2 SSEL1 00 31 30 P0 15 GPI...

Page 180: ...28 P0 30 GPIO Port 0 30 USB_D 1 Reserved Reserved 00 31 30 P0 31 GPIO Port 0 31 USB_D 2 Reserved Reserved 00 Table 131 Pin function select register 1 PINSEL1 address 0xE002 C004 bit description PINSEL...

Page 181: ...10 Function when 11 Reset value 1 0 P1 16 GPIO Port 1 16 ENET_MDC Reserved Reserved 00 3 2 P1 17 GPIO Port 1 17 ENET_MDIO Reserved Reserved 00 5 4 P1 18 GPIO Port 1 18 USB_UP_LED1 PWM1 1 CAP1 0 00 7 6...

Page 182: ...7 GPIO Port 2 7 RD2 RTS1 TRACEPKT2 1 00 17 16 P2 8 GPIO Port 2 8 TD2 TXD2 TRACEPKT3 1 00 19 18 P2 9 GPIO Port 2 9 USB_CONN ECT1 RXD2 EXTIN0 1 00 21 20 P2 10 GPIO Port 2 10 EINT0 Reserved Reserved 00...

Page 183: ...460 68 70 78 see Table 9 137 11 10 P2 5 GPIO Port 2 5 PWM1 6 DTR1 TRACEPKT0 1 LCDLP 00 13 12 P2 6 GPIO Port 2 6 PCAP1 0 RI1 TRACEPKT1 1 LCDVD 0 LCDVD 4 00 15 14 P2 7 GPIO Port 2 7 RD2 RTS1 TRACEPKT2 1...

Page 184: ...Reserved 00 27 26 P2 29 GPIO Port 2 29 DQMOUT1 Reserved Reserved 00 29 28 P2 30 Reserved Reserved Reserved Reserved 00 31 30 P2 31 Reserved Reserved Reserved Reserved 00 Table 137 LPC2420 60 68 70 78...

Page 185: ...ion select register 6 PINSEL6 address 0xE002 C018 bit description PINSEL6 Pin name Function when 00 Function when 01 Function when 10 Function when 11 Reset value 1 0 P3 0 GPIO Port 3 0 D0 Reserved Re...

Page 186: ...rved Reserved Reserved 00 31 30 P3 31 Reserved Reserved Reserved Reserved 00 Table 140 LPC24520 60 68 70 78 pin function select register 7 PINSEL7 address 0xE002 C01C bit description PINSEL7 Pin name...

Page 187: ...0 9 8 P4 4 GPIO Port 4 4 A4 Reserved Reserved 00 11 10 P4 5 GPIO Port 4 5 A5 Reserved Reserved 00 13 12 P4 6 GPIO Port 4 6 A6 Reserved Reserved 00 15 14 P4 7 GPIO Port 4 7 A7 Reserved Reserved 00 17 1...

Page 188: ...select register 9 PINSEL9 address 0xE002 C024 bit description PINSEL9 Pin name Function when 00 Function when 01 Function when 10 Function when 11 Reset value 1 0 P4 16 GPIO Port 4 16 A16 Reserved Res...

Page 189: ...ware should not write 1 to these bits NA Table 145 Pin function select register 11 PINSEL11 address 0xE002 C02C bit description Bit Symbol Value Description Reset value 0 LCDPE LCD Port Enable 0 0 LCD...

Page 190: ...6 to 31 For details see Section 9 4 Pin mode select register values 5 17 Pin Mode select register 4 PINMODE4 0xE002 C050 This register controls pull up pull down resistor configuration for PORT2 pins...

Page 191: ...details see Section 9 4 Pin mode select register values Table 150 Pin Mode select register 4 PINMODE4 address 0xE002 C050 bit description PINMODE4 Symbol Description Reset value 1 0 P2 00MODE PORT2 pi...

Page 192: ...egister values Table 154 Pin Mode select register 8 PINMODE8 address 0xE002 C060 bit description PINMODE8 Symbol Description Reset value 1 0 P4 00MODE PORT4 pin 0 on chip pull up down resistor control...

Page 193: ...able GPIO interrupts in IO0 2IntEnR Table 10 176 or IO0 2IntEnF Table 10 177 Interrupts are enabled in the VIC using the VICIntEnable register Table 7 106 3 Features 3 1 Digital I O ports GPIO PORT0 a...

Page 194: ...PB bus 3 2 Interrupt generating digital ports PORT0 and PORT2 provide an interrupt for each port pin Each port pin can be programmed to generate an interrupt on a rising edge a falling edge or both Ed...

Page 195: ...group of bits in a single GPIO port independently from other bits in the same port When PORT0 and PORT1 are used user must select whether these ports will be accessed via registers that provide enhan...

Page 196: ...ort s pins will be set to the desired level instantaneously R W NA IO0PIN 0xE002 8000 IO1PIN 0xE002 8010 IOSET GPIO Port Output Set register This register controls the state of output pins in conjunct...

Page 197: ...s register regardless of pin direction or alternate function selection as long as pins are not configured as an input to ADC The value read is masked by ANDing with inverted FIOMASK Writing to this re...

Page 198: ...lue 1 PORTn Register Address Name IntEnR GPIO Interrupt Enable for Rising edge R W 0x0 IO0IntEnR 0xE002 8090 IO2IntEnR 0xE002 80B0 IntEnF GPIO Interrupt Enable for Falling edge R W 0x0 IO0IntEnR 0xE00...

Page 199: ...n Register Address Name FIOxDIR0 Fast GPIO Port x Direction control register 0 Bit 0 in FIOxDIR0 register corresponds to pin Px 0 bit 7 to pin Px 7 8 byte R W 0x00 FIO0DIR0 0x3FFF C000 FIO1DIR0 0x3FFF...

Page 200: ...n output is unchanged 0x0 1 Controlled pin output is set to HIGH Table 165 Fast GPIO port output Set register FIO 0 1 2 3 4 SET address 0x3FFF C0 1 3 5 7 9 8 bit description Bit Symbol Value Descripti...

Page 201: ...ast GPIO Port x output Set Lower half word register Bit 0 in FIOxSETL register corresponds to pin Px 0 bit 15 to pin Px 15 16 half word R W 0x0000 FIO0SETL 0x3FFF C018 FIO1SETL 0x3FFF C038 FIO2SETL 0x...

Page 202: ...nd half word accessible register description Generic Register name Description Register length bits access Reset value PORTn Register Address Name FIOxCLR0 Fast GPIO Port x output Clear register 0 Bit...

Page 203: ...he current content of the Fast GPIO port pin value register Aside from the 32 bit long and word only accessible FIOPIN register every fast GPIO port can also be controlled via several byte and half wo...

Page 204: ...8 byte R W 0x00 FIO0PIN0 0x3FFF C014 FIO1PIN0 0x3FFF C034 FIO2PIN0 0x3FFF C054 FIO3PIN0 0x3FFF C074 FIO4PIN0 0x3FFF C094 FIOxPIN1 Fast GPIO Port x Pin value register 1 Bit 0 in FIOxPIN1 register corr...

Page 205: ...OxMASK0 Fast GPIO Port x Mask register 0 Bit 0 in FIOxMASK0 register corresponds to pin Px 0 bit 7 to pin Px 7 8 byte R W 0x0 FIO0MASK0 0x3FFF C010 FIO1MASK0 0x3FFF C030 FIO2MASK0 0x3FFF C050 FIO3MASK...

Page 206: ...set value 0 P0Int 0 PORT0 GPIO interrupt pending There are no pending interrupts on PORT0 0 1 There is at least one pending interrupt on PORT0 1 Reserved The value read from a reserved bit is not defi...

Page 207: ...P0xREI and P2xREI 0 Rising Edge Interrupt status Bit 0 in IOxIntStatR corresponds to pin Px 0 bit 31 in IOxIntStatR corresponds to pin Px 31 Rising edge has not been detected on the corresponding pin...

Page 208: ...R register sets pin P0 7 back to low level 7 2 Example 2 an instantaneous output of 0s and 1s on a GPIO port Write access to port s IOSET followed by write to the IOCLR register results with pins outp...

Page 209: ...a group of port s pins application must logically AND readout from the IOPIN with mask containing 0s in bits corresponding to pins that will be changed and 1s for all others Finally this result has to...

Page 210: ...include a generous suite of control registers half or full duplex operation flow control control frames hardware acceleration for transmit retry receive packet filtering and wake up on LAN activity Au...

Page 211: ...Advanced High performance bus CRC Cyclic Redundancy Check DMA Direct Memory Access Double word 64 bit entity FCS Frame Check Sequence CRC Fragment A part of an Ethernet frame one or multiple fragments...

Page 212: ...r management support allows system wake up using the receive filters or a magic frame detection filter Physical interface Attachment of external PHY chip through standard Media Independent Interface M...

Page 213: ...he OSI reference model see IEEE std 802 3 The MAC sublayer offers the service of transmitting and receiving frames to the next higher protocol level the MAC client layer typically the Logical Link Con...

Page 214: ...by software In half duplex mode the flow control module will generate back pressure by sending out continuous preamble only interrupted by pauses to prevent the jabber limit from being exceeded The Et...

Page 215: ...ceived frame The base address registers for the descriptor array registers indicating the number of descriptor array entries and descriptor array input output pointers are contained in the Ethernet bl...

Page 216: ...gnals used for connecting the Media Independent Interface MII and Table 11 184 shows the signals used for connecting the Reduced Media Independent Interface RMII to the external PHY Fig 27 Ethernet pa...

Page 217: ...effects The register map consists of registers in the Ethernet MAC and registers around the core for controlling DMA transfers flow control and filtering Reading from reserved addresses or reserved b...

Page 218: ...40 R W Station Address 0 register SA1 0xFFE0 0044 R W Station Address 1 register SA2 0xFFE0 0048 R W Station Address 2 register 0xFFE0 004C to 0xFFE0 00FC Reserved user software should not write ones...

Page 219: ...tware should not write ones to reserved bits The value read from a reserved bit is not defined Rx filter registers RxFliterCtrl 0xFFE0 0200 Receive filter control register RxFilterWoLStatus 0xFFE0 020...

Page 220: ...earing this bit results in normal operation 0 7 5 Unused 0x0 8 RESET TX Setting this bit will put the Transmit Function logic in reset 0 9 RESET MCS TX Setting this bit resets the MAC Control Sublayer...

Page 221: ...NFORCEMENT When enabled set to 1 the MAC will verify the content of the preamble to ensure it contains 0x55 and is error free A packet with an incorrect preamble is discarded When disabled no preamble...

Page 222: ...1d which represents the minimum IPG of 960 ns in 100 Mbps mode or 9 6 s in 10 Mbps mode In Half Duplex the recommended setting is 0x12 18d which also represents the minimum IPG of 960 ns in 100 Mbps m...

Page 223: ...rd specifies the attemptLimit to be 0xF 15d See IEEE 802 3 4 2 3 2 5 0xF 7 4 Reserved User software should not write ones to reserved bits The value read from a reserved bit is not defined 0x0 13 8 CO...

Page 224: ...1 3 Unused 0x0 Table 196 MII Mgmt Configuration register MCFG address 0xFFE0 0020 bit description Bit Symbol Function Reset value 0 SCAN INCREMENT Set this bit to cause the MII Management hardware to...

Page 225: ...lue 0 READ This bit causes the MII Management hardware to perform a single Read cycle The Read data is returned in Register MRDD MII Mgmt Read Data 0 1 SCAN This bit causes the MII Management hardware...

Page 226: ...n the packet please refer to Figure 11 27 7 1 16 Station Address 1 Register SA1 0xFFE0 0044 The Station Address 1 register SA1 has an address of 0xFFE0 0044 The bit definition of this register is show...

Page 227: ...TION ADDRESS 4th octet This field holds the fourth octet of the station address 0x0 15 8 STATION ADDRESS 3rd octet This field holds the third octet of the station address 0x0 31 16 Unused 0x0 Table 20...

Page 228: ...o memory The status also transitions to inactive if the transmit queue is empty or if the receive queue is full and status and data have been committed to memory 7 2 3 Receive Descriptor Base Address...

Page 229: ...rray for which RxDescriptor is the base address The number of descriptors should match the number of statuses The register uses minus one encoding i e if the array has 8 elements the value in the regi...

Page 230: ...ould increment the RxConsumeIndex The value must be wrapped to 0 once the value of RxDescriptorNumber has been reached If the RxProduceIndex equals RxConsumeIndex 1 the array is full and any further f...

Page 231: ...re transmit driver The transmit descriptor array is empty as long as TxProduceIndex equals TxConsumeIndex If the transmit hardware is enabled it will start transmitting frames as soon as the descripto...

Page 232: ...y through the frame descriptors The status register contents are valid as long as the internal status of the MAC is valid and should typically only be read when the transmit and receive processes are...

Page 233: ...is a Read Only register with an address of 0xFFE0 0160 The receive status vector register stores the most recent receive status returned by the MAC This register is provided for debug purposes because...

Page 234: ...vent seen was not long enough to be a valid packet 0 18 Carrier event previously seen Indicates that at some time since the last receive statistics a carrier event was detected 0 19 Receive code viola...

Page 235: ...backpressure cycles 0x0 Table 222 Flow Control Status register FlowControlStatus address 0xFFE0 8174 bit description Bit Symbol Function Reset value 15 0 MirrorCounterCurrent In full duplex mode this...

Page 236: ...h 0 13 RxFilterEnWoL When set to 1 the result of the perfect address matching filter and the imperfect hash filter will generate a WoL interrupt when there is a match 0 31 14 Unused 0x0 Table 223 Rece...

Page 237: ...rrupt status register bit definition is shown in Table 11 228 Note that all bits are flip flops with an asynchronous set in order to be able to generate interrupts if there are wake up events while cl...

Page 238: ...errupt set on a fatal underrun error in the transmit queue The fatal interrupt should be resolved by a Tx soft reset The bit is not set when there is a nonfatal underrun error 0 5 TxErrorInt Interrupt...

Page 239: ...essed i e on the transition to the situation where ProduceIndex ConsumeIndex 0 7 TxDoneIntEn Enable for interrupt triggered when a descriptor has been transmitted while the Interrupt bit in the Contro...

Page 240: ...more fragments Each fragment corresponds to a single descriptor The DMA managers in the Ethernet block scatter for receive and gather for transmit multiple fragments for a single Ethernet frame 8 1 Re...

Page 241: ...dex and RxProduceIndex define the descriptor locations that will be used next by hardware and software Both registers act as counters starting at 0 and wrapping when they reach the value of RxDescript...

Page 242: ...alculated once then held for every fragment of the same frame The concatenation of the two CRCs is shown in Table 11 236 Table 233 Receive Descriptor Fields Symbol Address offset Bytes Description Pac...

Page 243: ...ffer has 8 bytes the RxSize value will be 7 17 11 Unused 18 ControlFrame Indicates this is a control frame for flow control either a pause frame or a frame with an unsupported opcode 19 VLAN Indicates...

Page 244: ...is enabled the TxDescriptor TxStatus and TxDescriptorNumber registers should not be modified Two registers TxConsumeIndex and TxProduceIndex define the descriptor locations that will be used next by...

Page 245: ...4 4 Control information see Table 11 239 Table 239 Transmit descriptor control word Bit Symbol Description 10 0 Size Size in bytes of the data buffer This is the size of the frame or fragment as it ne...

Page 246: ...the software driver has to set up the appropriate Control registers and a descriptor to point to the packet data buffer before transferring the packet to hardware by incrementing the TxProduceIndex r...

Page 247: ...there is an AHB read access to a write only register likewise a write error is returned when there is an AHB write access to the read only register An AHB read or write error will be returned on AHB...

Page 248: ...escriptor is owned either by the device driver or by the Ethernet hardware Only the owner of a descriptor reads or writes its value Typically the sequence of use and ownership of descriptors and statu...

Page 249: ...at the value of the produce index and consume index An array must have at least 2 elements to be able to indicate a full descriptor array with a produce index of value 0 and a consume index of value 1...

Page 250: ...Depending on the PHY the software needs to initialize registers in the PHY via the MII Management interface The software can read and write PHY registers by programming the MCFG MCMD MADR registers of...

Page 251: ...ommand register before enabling the receive datapath in the MAC by setting the RECEIVE ENABLE bit in the MAC1 register The transmit DMA engine can be enabled at any time by setting the TxEnable bit in...

Page 252: ...dware still needs to process frames from the descriptor array the TxStatus bit in the Status register will return to 1 active Tx DMA manager reads the Tx descriptor array When the TxEnable bit is set...

Page 253: ...ents of the frame are still read via the AHB interface After an error the remaining transmit data is discarded by the Ethernet block If there are errors during transmission of a multi fragment frame t...

Page 254: ...LateCollision ExcessiveCollision ExcessiveDefer or Underrun error the transmission of the erroneous frame will be aborted remaining transmission data and frame fragments will be discarded and transmis...

Page 255: ...of four descriptors is allocated the array is 4x2x4 bytes and aligned on a 4 byte address boundary Since the number of descriptors matches the number of statuses the status array consists of four ele...

Page 256: ...array describes the remaining 4 bytes of the frame In the third descriptor the Last bit in the Control word is set to true 1 to indicate it is the last descriptor in the frame In this example the Int...

Page 257: ...For an RMII PHY the data communication between the Ethernet block and the PHY is communicated at half the data width 2 bits and twice the clock frequency 50 MHz In 10 Mbps mode data will only be tran...

Page 258: ...nly updated after the fragment data and the fragment status information has been committed to memory which is checked by an internal tag protocol in the memory interface The Rx DMA manager continues t...

Page 259: ...ror LengthError SymbolError CRCError or NoDescriptor error nonfatal overrun errors are reported in the RxError bit of the IntStatus register fatal Overrun errors are report in the RxOverrun bit of the...

Page 260: ...ts or if a nonfatal data Overrun occurred the hardware will set the RxErrorInt bit of the IntStatus register All of the above interrupts can be enabled and disabled by setting or resetting the corresp...

Page 261: ...is stored in the Packet field of the descriptors The number of bytes in the fragment buffer is stored in the Size field of the descriptor Control word The Interrupt field in the Control word of the de...

Page 262: ...buffer the status for the first fragment buffer will be written and the Rx DMA will continue filling the second fragment buffer Since this is a multi fragment receive the status of the first fragment...

Page 263: ...LateCollision error the remaining data in the transmit frame will be discarded The Ethernet block will set the Error and LateCollision bits in the frame s status fields The TxError bit in the IntStat...

Page 264: ...ns when the it receives a pause frame Rx flow control is initiated by the receiving side of the transmission It is enabled by setting the RX FLOW CONTROL bit in the MAC1 configuration register If the...

Page 265: ...than register PauseTimer 15 0 to ensure an early expiration of the mirror counter allowing time to send a new pause frame before the transmission on the other side can resume By continuing to send pau...

Page 266: ...pause frame transmission completes the internal mirror counter will start counting bit slots as soon as the counter reaches the value in the MirrorCounter field another pause frame is transmitted Whil...

Page 267: ...an 64 bytes a promiscuous mode allows all packets to be passed to software Overview The Ethernet block has the capability to filter out receive frames by analyzing the Ethernet destination address in...

Page 268: ...rames of types unicast multicast and broadcast respectively to be accepted ignoring the Ethernet destination address in the frame To program promiscuous mode i e to accept all frames set all 3 bits to...

Page 269: ...t hash filter can be applied to multicast addresses by setting the AcceptMulticastHashEn bit in the RxFilter register to 1 The same imperfect hash filter that is available for multicast addresses can...

Page 270: ...son for a Wake up event Before going to power down the power management software should clear the register by writing the RxFilterWolClear register NOTE when entering in power down mode a receive fram...

Page 271: ...in the IntStatus register the MagicPacketWoL bit is set in the RxFilterWoLStatus register Software can reset the bit writing a 1 to the corresponding bit of the RxFilterWoLClear register Example An ex...

Page 272: ...s full the state machine will return to the INACTIVE state For the state machine in Figure 11 34 a soft reset is like a hardware reset assertion i e after a soft reset the receive datapath is inactive...

Page 273: ...bytes CRC Frame Check Sequence FCS Padding is affected by the value of the AUTO DETECT PAD ENABLE ADPEN VLAN PAD ENABLE VLPEN and PAD CRC ENABLE PADEN bits of the MAC2 configuration register as well a...

Page 274: ...the RxSize fields from the receive status arrays will be valid Frame lengths are checked by comparing the length type field of the frame to the actual number of bytes in the frame A LengthError is re...

Page 275: ...RESET Rx Setting this bit will reset the receive function in the MAC The value after a hardware reset assertion is 0 RESET MCS Tx Setting this bit will reset the MAC Control Sublayer pause frame logi...

Page 276: ...er software has to Disable the receive function by resetting the RECEIVE ENABLE bit in the MAC1 configuration register and resetting of the RxEnable bit of the Command register Set the RESET MCS Rx bi...

Page 277: ...HY is via either MII or RMII An MII operates at 25 MHz transferring a byte in 2 clock cycles An RMII operates at 50 MHz transferring a byte in 4 clock cycles The data transfer rate is the same in both...

Page 278: ...unction 9 23 3 Overall bandwidth Overall traffic on the AHB is the sum of DMA access rates and CPU access rates which comes to approximately 66 5 MB s The peak bandwidth requirement can be somewhat hi...

Page 279: ...608EDB8 else q0 0x00000000 crc crc 4 q3 q2 q1 q0 byte 4 return crc For FCS calculation this function is passed a pointer to the first byte of the frame and the length of the frame without the FCS For...

Page 280: ...monochrome LCD panels 4 Features AHB bus master interface to access frame buffer Setup and control via a separate AHB slave interface Dual 16 deep programmable 64 bit wide FIFOs for buffering incomin...

Page 281: ...of lines per panel Number of pixel clocks per line Hardware cursor control Signal polarity active HIGH or LOW AC panel bias Panel clock frequency Bits per pixel Display type STN monochrome STN color o...

Page 282: ...f the following color modes 1 bpp palettized 2 colors selected from available colors 2 bpp palettized 4 colors selected from available colors 4 bpp palettized 16 colors selected from available colors...

Page 283: ...ther chip functions In Table 12 242 only the LCD related portion of the pin name is shown Remark To enable the LCD controller see Section 9 5 12 5 1 Signal usage The signals that are used for various...

Page 284: ...TN displays Pin name 4 bit Monochrome 10 pins 8 bit Monochrome 14 pins Color 14 pins Table 244 Pins used for dual panel STN displays Pin name 4 bit Monochrome 14 pins 8 bit Monochrome 22 pins Color 22...

Page 285: ...The hardware coded gray scale algorithm logic sequences the activity of the addressed pixels over a programmed number of frames to provide the effective display appearance For TFT displays either an...

Page 286: ...DMA access to display data stored in memory elsewhere in the system The LCD DMA controller can only access the 10 kB SRAM on AHB1 and the external memory 6 1 1 AMBA AHB slave interface The AHB slave i...

Page 287: ...the FIFOs have not completed their synchronization and updating sequence Fills up the DMA FIFOs in dual panel mode in an alternating fashion from a single DMA request Asserts the a bus error interrup...

Page 288: ...ted data formats the required data for each panel display pixel must be extracted from the data word Table 246 FIFO bits for Little endian Byte Little endian Pixel order FIFO bit 1 bpp 2 bpp 4 bpp 8 b...

Page 289: ...ian Byte Big endian Pixel order FIFO bit 1 bpp 2 bpp 4 bpp 8 bpp 16 bpp 24 bpp 31 p0 p0 p0 p0 p0 30 p1 29 p2 p1 28 p3 27 p4 p2 p1 26 p5 25 p6 p3 24 p7 23 p8 p4 p2 p1 p0 22 p9 21 p10 p5 20 p11 19 p12 p...

Page 290: ...B mode Table 248 FIFO bits for Little endian Byte Big endian Pixel order FIFO bit 1 bpp 2 bpp 4 bpp 8 bpp 16 bpp 24 bpp 31 p24 p12 p6 p3 p1 30 p25 29 p26 p13 28 p27 27 p28 p14 p7 26 p29 25 p30 p15 24...

Page 291: ...Blue 0 p1 Green 5 p1 Blue 2 25 p1 Green 4 p1 Green 4 p1 Blue 1 24 p1 Green 3 p1 Green 3 p1 Blue 0 23 p0 Blue 7 p1 Green 2 p1 Green 2 p1 Green 3 22 p0 Blue 6 p1 Green 1 p1 Green 1 p1 Green 2 21 p0 Blue...

Page 292: ...d as the TFT panel data The red and blue pixel data can be swapped to support BGR data format using a control register bit bit 8 BGR See the LCD_CTRL register description for more information Table 12...

Page 293: ...a read write port to the cursor image RAM 6 5 1 Cursor operation The hardware cursor is contained in a dual port RAM It is programmed by software through the AHB slave interface The AHB slave interfac...

Page 294: ...le 12 253 6 5 3 Cursor movement The following descriptions assume that both the screen and cursor origins are at the top left of the visible screen the first visible pixel scanned each frame Figure 12...

Page 295: ...automatically at the screen limits when it extends beyond the screen image to the right or bottom see X1 Y1 in Figure 12 38 The checked pattern shows the visible portion of the cursor Because the CRS...

Page 296: ...displayed cursor coordinate system is expressed in terms of X Y 64 x 64 is an extension of the 32 x 32 format shown in Figure 12 39 32 by 32 pixel format Four cursors are held in memory each with the...

Page 297: ...y 5 31 21 31 11 10 6 0 22 0 6 y 22 y 6 31 22 31 9 8 7 0 23 0 7 y 23 y 7 31 23 31 7 6 0 0 16 0 0 y 16 y 0 31 16 31 5 4 1 0 17 0 1 y 17 y 1 31 17 31 3 2 2 0 18 0 2 y 18 y 2 31 18 31 1 0 3 0 19 0 3 y 19...

Page 298: ...are used in STN mode to convert the gray scaler output to a parallel format as required by the display For monochrome displays this is either 4 or 8 bits wide and for color displays it is 8 bits wide...

Page 299: ...The CLKSEL bit in the LCD_POL register determines whether the base clock used is CCLK or the LCDCLKIN pin 6 9 Timing controller The primary function of the timing controller block is to generate the...

Page 300: ...bus error interrupt may be cleared by writing a 1 to the BERIC bit in the LCD_INTCLR register This action releases the master interface from its ERROR state to the start of FRAME state and enables fr...

Page 301: ...the signals in step 2 have stabilized the contrast voltage not controlled or supplied by the LCD controller is applied to the LCD panel 4 If required a software or hardware timer can be used to provid...

Page 302: ...rol register 0x0 R W 0xFFE1 0004 LCD_TIMV Vertical Timing Control register 0x0 R W 0xFFE1 0008 LCD_POL Clock and Signal Polarity Control register 0x0 R W 0xFFE1 000C LCD_LE Line End Control register 0...

Page 303: ...0xFFE1 0C08 CRSR_PAL0 Cursor Palette register 0 0x0 R W 0xFFE1 0C0C CRSR_PAL1 Cursor Palette register 1 0x0 R W 0xFFE1 0C10 CRSR_XY Cursor XY Position register 0x0 R W 0xFFE1 0C14 CRSR_CLIP Cursor Cli...

Page 304: ...to wait before starting the next display line HBP can generate a delay of 1 256 pixel clock cycles Program with desired value minus 1 0x0 23 16 HFP Horizontal front porch The 8 bit HFP field sets the...

Page 305: ...ble 12 262 Table 262 Vertical Timing register LCD_TIMV RW 0xFFE1 0004 Bits Function Description Reset value 31 24 VBP Vertical back porch This is the number of inactive lines at the start of a frame a...

Page 306: ...ith the number of lines required minus one The number of horizontal synchronization lines must be small for example program to zero for passive STN LCDs The higher the value the worse the contrast on...

Page 307: ...output pin is active HIGH in TFT mode 1 LCDENAB output pin is active LOW in TFT mode 0x0 13 IPC Invert panel clock The IPC bit selects the edge of the panel clock on which pixel data is driven out on...

Page 308: ...ce for LCDCLK 0 the clock source for the LCD block is CCLK 1 the clock source for the LCD block is LCDDCLK 0x0 4 0 PCD_LO Lower five bits of panel clock divisor The ten bit PCD field comprising PCD_HI...

Page 309: ..._LPBASE register is the color LCD lower panel DMA base address register and is used to program the base address of the frame buffer for the lower panel LCDLPBase must be initialized before enabling th...

Page 310: ...aligned 0x0 2 0 reserved Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined Table 267 LCD Control register LCD_CTRL RW 0xFFE1 0018 Bits Fu...

Page 311: ...yte ordering in memory 0 little endian byte order 1 big endian byte order 0x0 8 BGR Color format selection 0 RGB normal output 1 BGR red and blue swapped 0x0 7 LcdDual Single or Dual LCD panel selecti...

Page 312: ...0 16 bpp 5 6 5 mode 111 12 bpp 4 4 4 mode 0x0 0 LcdEn LCD enable control bit 0 LCD disabled Signals LCDLP LCDDCLK LCDFP LCDENAB and LCDLE are low 1 LCD enabled Signals LCDLP LCDDCLK LCDFP LCDENAB and...

Page 313: ...Function Description Reset value 31 5 reserved Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined 4 BERRAW AHB master bus error raw interr...

Page 314: ...t status Set when the both the BERRAW bit in the LCD_INTRAW register and the BERIM bit in the LCD_INTMSK register are set 0x0 3 VCompMIS Vertical compare masked interrupt status Set when the both the...

Page 315: ...Table 12 273 7 15 Color Palette registers LCD_PAL RW 0xFFE1 0200 to 0xFFE1 03FC The LCD_PAL register contain 256 palette entries organized as 128 locations of two entries per word 2 LNBUIC LCD next ad...

Page 316: ...ter see Cursor Configuration register description the cursor image RAM contains either four 32x32 cursor images or a single 64x64 cursor image The two colors defined for the cursor are mapped onto val...

Page 317: ...s currently being scanned The contents of the CRSR_CTRL register are described in Table 12 276 7 18 Cursor Configuration register CRSR_CFG RW 0xFFE1 0C04 The CRSR_CFG register provides overall configu...

Page 318: ...played according to the abilities of the LCD panel in the same way as the frame buffers palette output is displayed In monochrome STN mode only the upper 4 bits of the Red field are used In STN color...

Page 319: ...egister is 1 the displayed cursor image is only changed during the vertical frame blanking period providing that the cursor position has been updated since the Clip register was programmed When progra...

Page 320: ...sor When 0 the first displayed pixel is from the top line of the cursor image 0x0 7 6 reserved Reserved user software should not write ones to reserved bits The value read from a reserved bit is not d...

Page 321: ...RW 0xFFE1 0C28 Bits Function Description Reset value 31 1 reserved Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined 0 CrsrRIS Cursor raw...

Page 322: ...d used to produce LCDCLK 3 The duration of the LCDLP signal is controlled by the HSW field in the LCD_TIMH register 4 The Polarity of the LCDLP signal is determined by the IHS bit in the LCD_POL regis...

Page 323: ...ntal timing for STN displays panel data clock active 1 The active data lines will vary with the type of TFT panel 2 The LCD panel clock is selected and scaled by the LCD controler and used to produce...

Page 324: ...rch defined in line clocks pixel data and horizontal control signals for one frame one frame all horizontal lines for one frame see horizontal timing for TFT displays data enable LCDDCLK panel clock p...

Page 325: ...LCDDCLK P2 2 1 LCDDCLK P2 2 1 LCDDCLK P2 2 1 LCDDCLK LCDLE P2 1 1 LCDLE P2 1 1 LCDLE P2 1 1 LCDLE LCDPWR P2 0 1 CDPWR P2 0 1 LCDPWR P2 0 1 LCDPWR LCDCLKIN P2 11 2 LCDCLKIN P2 11 2 LCDCLKIN P2 0 2 LCD...

Page 326: ...R P2 0 1 LCDPWR LCDCLKIN P2 11 2 LCDCLKIN P2 11 2 LCDCLKIN P2 11 2 LCDCLKIN Table 287 LCD panel connections for STN dual panel mode External pin 4 bit mono STN dual panel 8 bit mono STN dual panel Col...

Page 327: ...6 1 RED0 P2 6 1 RED1 P2 6 1 RED1 P2 6 1 RED4 LCDVD 3 P2 12 2 RED0 P4 29 3 RED0 P4 29 3 RED3 LCDVD 2 P4 28 3 intensity P4 28 3 RED2 LCDVD 1 P0 5 5 RED1 LCDVD 0 P0 4 5 RED0 LCDLP P2 5 1 LCDLP P2 5 1 LC...

Page 328: ...ation of the devices All transactions are initiated by the host controller The host schedules transactions in 1 ms frames Each frame contains a Start Of Frame SOF marker and transactions that transfer...

Page 329: ...onfiguration Table 13 290 shows the supported endpoint configurations Endpoints are realized and configured at run time using the Endpoint realization registers documented in Section 13 9 5 Endpoint r...

Page 330: ...3 Yes 6 13 Isochronous In 1 to 1023 Yes 7 14 Interrupt Out 1 to 64 No 7 15 Interrupt In 1 to 64 No 8 16 Bulk Out 8 16 32 64 Yes 8 17 Bulk In 8 16 32 64 Yes 9 18 Isochronous Out 1 to 1023 Yes 9 19 Isoc...

Page 331: ...recognition and handshake evaluation generation 5 3 Endpoint RAM EP_RAM Each endpoint buffer is implemented as an SRAM based FIFO The SRAM dedicated for this purpose is called the EP_RAM Each realized...

Page 332: ...3 3V Software can then control the CONNECT signal by writing to the CON bit using the SIE Set Device Status command 5 8 GoodLink Good USB connection indication is provided through GoodLink technology...

Page 333: ...evice interface can be routed to either USB port1 using USB_CONNECT1 USB_UP_LED1 USB_D 1 USB_D 1 or USB port2 using USB_CONNECT2 USB_UP_LED2 USB_D 2 USB_D 2 to allow for more versatile pin multiplexin...

Page 334: ...SBClkSt registers are provided When software wishes to access the device controller registers it should first ensure usbclk is enabled by setting DEV_CLK_EN in the USBClkCtrl register and then poll th...

Page 335: ...ice Controller registers directly accessible by the CPU The Serial Interface Engine SIE has other registers that are indirectly accessible via the SIE command registers See Section 13 11 Serial interf...

Page 336: ...0 USBCmdData USB Command Data RO 0x0000 0000 0xFFE0 C214 DMA registers USBDMARSt USB DMA Request Status RO 0x0000 0000 0xFFE0 C250 USBDMARClr USB DMA Request Clear WO 3 0x0000 0000 0xFFE0 C254 USBDMAR...

Page 337: ...USBClkSt If it is set then software can go ahead with the register access Software does not have to repeat this exercise for every access provided that the USBClkCtrl bits are not disturbed USBClkSt...

Page 338: ...t write ones to reserved bits The value read from a reserved bit is not defined NA 1 DEV_CLK_ON Device clock on The usbclk input to the device controller is active 0 2 Reserved user software should no...

Page 339: ...efined NA 31 EN_USB_INTS Enable all USB interrupts When this bit is cleared the Vectored Interrupt Controller does not see the ORed output of the USB interrupt lines 1 Table 297 USB Interrupt Status r...

Page 340: ...Set when Realize Endpoint register USBReEp or MaxPacketSize register USBMaxPSize is updated and the corresponding operation is completed 0 9 ERR_INT Error Interrupt Any bus error interrupt from the US...

Page 341: ...AT EP_SLOW EP_FAST FRAME Table 303 USB Device Interrupt Clear register USBDevIntClr address 0xFFE0 C208 bit description Bit Symbol Value Description Reset value 31 0 See USBDevIntClr bit allocation ta...

Page 342: ...ansmitted or when a NAK handshake is sent on the bus and the interrupt on NAK feature is enabled see Section 13 11 3 Set Mode Command 0xF3 Data write 1 byte on page 364 A bit set to one in this regist...

Page 343: ...Received Interrupt bit 0 9 EP4TX Endpoint 4 Data Transmitted Interrupt bit or sent a NAK 0 10 EP5RX Endpoint 5 Data Received Interrupt bit 0 11 EP5TX Endpoint 5 Data Transmitted Interrupt bit or sent...

Page 344: ...but using USBEpIntClr is recommended because of its ease of use Each physical endpoint has its own reserved bit in this register The bit field definition is the same as that of USBEpIntSt shown in Ta...

Page 345: ...3 12 11 10 9 8 Symbol EP7TX EP7RX EP6TX EP6RX EP5TX EP5RX EP4TX EP4RX Bit 7 6 5 4 3 2 1 0 Symbol EP3TX EP3RX EP2TX EP2RX EP1TX EP1RX EP0TX EP0RX Table 312 USB Endpoint Interrupt Clear register USBEpIn...

Page 346: ...ader showing the size of the packet length received The EP_ RAM space in words required for the physical endpoint can be expressed as where dbstatus 1 for a single buffered endpoint and 2 for double a...

Page 347: ...ee Section 13 9 5 1 Realization of endpoints is a multi cycle operation Pseudo code for endpoint realization is shown below Clear EP_RLZED bit in USBDevIntSt for every endpoint to be realized OR with...

Page 348: ...endpoint number Writing to USBMaxPSize will set the array element pointed to by USBEpIn USBEpIn is a write only register 9 5 4 USB MaxPacketSize register USBMaxPSize 0xFFE0 C24C On reset the control...

Page 349: ...m the USB bus will be available in the least significant byte of USBRxData USBRxData is a read only register 9 6 2 USB Receive Packet Length register USBRxPLen 0xFFE0 C220 This register contains the n...

Page 350: ...ze software should submit data in packets of MaxPacketSize and send the remaining extra bytes in the last packet For example if the MaxPacketSize is 64 bytes and the data buffer to be transferred is o...

Page 351: ...iption Bit Symbol Value Description Reset value 9 0 PKT_LNGTH The remaining number of bytes to be written to the selected endpoint buffer This field is decremented by 4 by hardware after each write to...

Page 352: ...The DMA cannot be enabled for control endpoints EP0 and EP1 USBDMARSt is a read only register Table 326 USB Command Code register USBCmdCode address 0xFFE0 C210 bit description Bit Symbol Value Descri...

Page 353: ...DMA request This can be useful when switching from Slave to DMA mode of operation for an endpoint if a packet to be processed in DMA mode arrives before the corresponding bit of USBEpIntEn is cleared...

Page 354: ...SBEpDMASt is a read only register Table 331 USB DMA Request Set register USBDMARSet address 0xFFE0 C258 bit description Bit Symbol Value Description Reset value 0 EP0 0 Control endpoint OUT DMA cannot...

Page 355: ...USBEpDMADis is a write only register 9 8 8 USB DMA Interrupt Status register USBDMAIntSt 0xFFE0 C290 Each bit of this register reflects whether any of the 32 bits in the corresponding interrupt status...

Page 356: ...of Transfer Interrupt bit 0 0 All bits in the USBEoTIntSt register are 0 1 At least one bit in the USBEoTIntSt is set 1 NDDR New DD Request Interrupt bit 0 0 All bits in the USBNDDRIntSt register are...

Page 357: ...it description Bit Symbol Value Description Reset value 31 0 EPxx Endpoint xx 2 xx 31 End of Transfer Interrupt request 0 0 There is no End of Transfer interrupt request for endpoint xx 1 There is an...

Page 358: ...terrupt Clear register USBSysErrIntClr 0xFFE0 C2BC Writing one to a bit in this register clears the corresponding bit in the USBSysErrIntSt register Writing zero has no effect USBSysErrIntClr is a wri...

Page 359: ...EpIntEn register the corresponding status bit in the USBEpIntSt is set For non isochronous endpoints all endpoint interrupt events are divided into two types by the corresponding USBEpIntPri n registe...

Page 360: ...t event occurs on a non control endpoint and the endpoint interrupt is not enabled in the USBEpIntEn register the corresponding status bit in the USBDMARSt is set by hardware This serves as a flag for...

Page 361: ...t shown Fig 47 Interrupt event handling USB_INT_REQ_HP USB_INT_REQ_LP USB_INT_REQ_DMA EN_USB_INTS to VIC channel 22 FRAME EP_FAST EP_SLOW USBDevIntPri 0 USBDevIntPri 1 USBEpIntPri n USBEpIntSt USBDMAR...

Page 362: ...d corresponds to On completion of the read the CDFULL bit of USBDevInSt will be set indicating the data is available for reading in the USBCmdData register In the case of multi byte registers the leas...

Page 363: ...ce D0 Write 1 byte Configure Device Device D8 Write 1 byte Set Mode Device F3 Write 1 byte Read Current Frame Number Device F5 Read 1 or 2 bytes Read Test Register Device FD Read 2 bytes Set Device St...

Page 364: ...D_CLK is fixed to 1 the 48 MHz clock cannot be stopped when the device enters suspend state 1 INAK_CI Interrupt on NAK for Control IN endpoint 0 0 Only successful transactions generate an interrupt 1...

Page 365: ...Device Status Register Table 351 Set Device Status Register bit description Bit Symbol Value Description Reset value 0 CON The Connect bit indicates the current connect status of the device It contro...

Page 366: ...into the suspended state The device is disconnected The device receives resume signalling on its upstream port This bit is cleared when read 0 0 SUS bit not changed 1 SUS bit changed At the same time...

Page 367: ...fication 0100 Error in Token CRC 0101 Error in Data CRC 0110 Time Out Error 0111 Babble 1000 Error in End of Packet 1001 Sent Received NAK 1010 Sent Stall 1011 Buffer Overrun Error 1100 Sent Empty Pac...

Page 368: ...atus of B_1_FULL 0 0 For an IN endpoint at least one write endpoint buffer is empty 1 For an OUT endpoint at least one endpoint read buffer is full 1 ST Stalled endpoint indicator 0 0 The selected end...

Page 369: ...he buffer 2 status 0 0 Buffer 2 is empty 1 Buffer 2 is full 7 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined NA Table 354 Select Endpoi...

Page 370: ...e Section 13 13 Slave mode operation for a description of when this command is used 11 14 Validate Buffer Command 0xFA Data none When the CPU has written data into an IN buffer software should issue a...

Page 371: ...e PLL setting and configuration see Section 4 3 2 12 Procedure for determining PLL settings 3 Enable the device controller clocks by setting DEV_CLK_EN and AHB_CLK_EN bits in the USBClkCtrl register P...

Page 372: ...ansfers data between RAM and the endpoint buffer using the Register Interface 13 1 Interrupt generation In slave mode data packet transfer between RAM and an endpoint buffer can be initiated in respon...

Page 373: ...ise an empty packet will be sent in the next frame If the software clears WR_EN before the entire packet is written writing will start again from the beginning the next time WR_EN is set for this endp...

Page 374: ...lustrates the UDCA and its relationship to the UDCA Head USBUDCAH register and DMA Descriptors 14 3 Triggering the DMA engine An endpoint raises a DMA request when Slave mode is disabled by setting th...

Page 375: ...for non isochronous endpoints are four words long DDs for isochronous endpoints are five words long The parameters associated with a DMA transfer are The start address of the DMA buffer The length of...

Page 376: ...When set this bit indicates that the descriptor belongs to an isochronous endpoint Hence 5 words have to be read when fetching it 14 4 5 Max_packet_size The maximum packet size of the endpoint This pa...

Page 377: ...rviced At least one packet is transferred NormalCompletion The DD is retired because the end of the buffer is reached and there were no errors The DD_retired bit is also set DataUnderrun Before reachi...

Page 378: ...s from the first byte of the first packet 14 4 15 Isochronous_packetsize_memory_address The memory buffer address where the packet size information along with the frame number has to be transferred or...

Page 379: ...o the USB RAM memory locations starting from DMA_buffer_start_addr For IN endpoints the data is fetched from the USB RAM at DMA_buffer_start_addr and written to the EP_RAM The DMA_buffer_start_addr an...

Page 380: ...ng a No_Packet DD the DMA engine clears the DMA request bit in USBDMARSt corresponding to the endpoint without transferring a packet The DD is retired with a status code of NormalCompletion This can b...

Page 381: ...ket of size specified by this field is transferred from the USB device to the host and Isochronous_packet_size_memory_address is incremented by 4 at the end of the packet transfer If Packet_length is...

Page 382: ...arate DMA buffers This is achieved by setting the DMA mode to Auto Transfer Length Extraction ATLE mode in the DMA descriptor ATLE mode is supported for Bulk endpoints only OUT transfers in ATLE mode...

Page 383: ...t in the DMA_buffer_length field of the DD To ensure that both bytes of the DMA_buffer_length are extracted in the event they are split between two packets the flags LS_byte_extracted and MS_byte_extr...

Page 384: ...the last buffer length completes on a MaxPacketSize packet boundary the device software must program the next DD with DMA_buffer_length field 0 so that an empty packet is sent by the device to mark th...

Page 385: ...buffered endpoint operation The Bulk and Isochronous endpoints of the USB Device Controller are double buffered to increase data throughput When a double buffered endpoint is realized enough space fo...

Page 386: ..._2 The following example illustrates how double buffering works for a Bulk IN endpoint in Slave mode Assume that both buffer 1 B_1 and buffer 2 B_2 are empty and that the active buffer is B_1 The inte...

Page 387: ...For isochronous endpoints the active data buffer is switched by hardware when the FRAME interrupt occurs The SIE Clear Buffer and Validate Buffer commands do not cause the active buffer to be switche...

Page 388: ...troller and I2C The I2C interface controls the external OTG ATX The USB is a 4 wire bus that supports communication between a host and a number 127 max of peripherals The host controller allocates the...

Page 389: ...ntroller is shown below in Figure 14 51 3 Interfaces The OTG controller has two USB ports indicated by suffixes 1 and 2 in the USB pin names and referred to as USB port 1 U1 and USB port 2 U2 in the f...

Page 390: ...l clock External OTG transceiver USB_SDA1 I O I2C serial data External OTG transceiver USB_TX_E1 O Transmit enable External OTG transceiver USB_TX_DP1 O D transmit data External OTG transceiver USB_TX...

Page 391: ...lHeadED 0xFFE0 C020 R W Contains the physical address of the first endpoint descriptor of the control list 0x0 HcControlCurrentED 0xFFE0 C024 R W Contains the physical address of the current endpoint...

Page 392: ...nt for register definitions HcRhStatus 0xFFE0 C050 R W This register is divided into two parts The lower D word represents the hub status field and the upper word represents the hub status change fiel...

Page 393: ...C interface Master only controls an external OTG transceiver USB OTG On The Go is a supplement to the USB 2 0 specification that augments the capability of existing mobile devices and USB peripherals...

Page 394: ...TG controller is capable of operating in the following modes One port host and one port dual role device see Figure 15 53 One port host and one port device see Figure 15 55 Two port host see Figure 15...

Page 395: ...signal Control USB_INT1 I OTG ATX interrupt External OTG transceiver USB_SCL1 I O I2C serial clock External OTG transceiver USB_SDA1 I O I2C serial data External OTG transceiver USB_TX_E1 O Transmit e...

Page 396: ...P VM mode for OTG functionality and USB signalling see Figure 15 54 In both cases port U2 is connected as a host Solution one uses fewer pins Fig 53 USB OTG port configuration port U1 OTG Dual Role de...

Page 397: ...USB OTG controller Fig 54 USB OTG port configuration VP_VM mode USB_TX_DP1 USB_TX_DM1 USB_RCV1 USB_RX_DP1 USB_RX_DM1 USB_SCL1 USB_SDA1 SPEED ADR PSW SDA SCL RESET_N INT_N VP VM SUSPEND OE_N INT_N SE0_...

Page 398: ...USB as one port host and one port device Port U2 is connected as device and port U1 is connected as host using an embedded USB transceiver There is no OTG functionality on either port Fig 55 USB OTG p...

Page 399: ...ts wide and aligned to word address boundaries Fig 56 USB OTG port configuration port U1 host port U2 device USB_UP_LED1 USB_D 1 USB_D 1 USB_PWRD1 15 k 15 k LPC24XX USB A connector USB B connector 33...

Page 400: ...lkCtrl 0xFFE0 CFF4 R W OTG clock controller OTGClkSt 0xFFE0 CFF8 RO OTG clock status Table 362 USB OTG and I2C register address definitions Name Address Access Function Table 363 USB Interrupt Status...

Page 401: ...ponding bit in the OTGIntSt register Writing a zero has no effect The bit allocation of OTGIntClr is the same as in OTGIntSt 7 6 OTG Status and Control Register OTGStCtrl 0xFFE0 C110 The OTGStCtrl reg...

Page 402: ...ction 0 monoshot 1 free running 0 5 TMR_EN Timer enable When set TMR_CNT increments When cleared TMR_CNT is reset to 0 0 6 TMR_RST Timer reset Writing one to this bit resets TMR_CNT to 0 This provides...

Page 403: ...PORT_FUNC bit 1 0 Table 366 Port function truth table PORT_FUNC 0 0 PORT_FUNC 0 1 PORT_FUNC 1 0 U1 device OTG U2 host U1 host OTG U2 host PORT_FUNC 1 1 reserved U1 host U2 device DEVICE CONTROLLER HOS...

Page 404: ...3 OTG_CLK_EN OTG clock enable 0 0 Disable the OTG clock 1 Enable the OTG clock 4 AHB_CLK_EN AHB master clock enable 0 0 Disable the AHB clock 1 Enable the AHB clock 31 5 NA Reserved user software sho...

Page 405: ...n the byte read from the slave is not acknowledged That is the last byte of a master receive operation is not acknowledged 7 12 I2C Status Register I2C_STS 0xFFE0 C304 The I2C_STS register provides st...

Page 406: ...receive an acknowledge 3 DRMI Master Data Request Interrupt Once a transmission is started the transmitter must have data to transmit as long as it isn t followed by a stop condition or it will hold...

Page 407: ...0 TX FIFO is not full 1 TX FIFO is full 11 TFE Transmit FIFO Empty TFE is set when the TX FIFO is empty and is cleared when the TX FIFO contains valid data 1 0 TX FIFO contains valid data 1 TX FIFO i...

Page 408: ...FIFO i e not empty 0 0 Disable the DAI 1 Enable the DAI 7 TFFIE Transmit FIFO Not Full Interrupt Enable This enables the Transmit FIFO Not Full interrupt to indicate that the more data can be written...

Page 409: ...ification The EN_USB_INTS bit in the USBIntSt register enables the routing of any of the USB related interrupts to the VIC controller see Figure 15 58 Remark During the HNP switching between host and...

Page 410: ...The context of the OTG controller operation is shown in Figure 15 59 Each controller Host Device or OTG communicates with its software stack through a set of status and control registers and interrup...

Page 411: ...OTG software stack is responsible for implementing all of the states in the Dual Role B Device State Diagram The OTG controller hardware provides support for the state transitions between the states...

Page 412: ...Hardware support for B device switching from peripheral state to host state idle set HNP_SUCCESS set PORT_FUNC 0 drive J on internal host controller port and SE0 on U1 wait 25 s for bus to settle disc...

Page 413: ...ode examples that show how the actions in Figure 15 61 are accomplished The examples assume that ISP1301 is being used as the external OTG transceiver Remove D pull up Remove D pull up through ISP1301...

Page 414: ...NP switching In this case the role of the OTG controller is host A device and the A device switches roles from host to peripheral The On The Go Supplement defines the behavior of a dual role A device...

Page 415: ...s to the Dual Role A Device states is also shown A device states are shown in bold font with a circle around them Fig 62 Hardware support for A device switching from host state to peripheral state dis...

Page 416: ...de examples that show how the actions in Figure 15 63 are accomplished The examples assume that ISP1301 is being used as the external OTG transceiver Fig 63 State transitions implemented in software d...

Page 417: ...ISP1301 address R W 0 OTG_I2C_TX 0x005 Send Mode Control 1 Clear register address OTG_I2C_TX 0x210 Clear BDIS_ACON_EN bit send STOP condition Wait for TDI to be set while OTG_I2C_STS TDI Clear TDI OT...

Page 418: ...The OTG controller clocking is shown in Figure 15 64 A clock switch controls each clock with the exception of ahb_slave_clk When the enable of the clock switch is asserted its clock output is turned...

Page 419: ...CON bit is cleared in the SIE Get Device Status register Section 13 11 This signal allows DEV_CLK_EN to be cleared during normal operation when software does not need to access the Device controller r...

Page 420: ...atency associated with re enabling ahb_master_clk 2 ms after the last DMA access host_dma_need_clk is de asserted to help conserve power This signal allows AHB_CLK_EN to be cleared during normal opera...

Page 421: ...C24XX USB OTG controller 4 Enable the desired USB pin functions by writing to the corresponding PINSEL registers 5 Follow the appropriate steps in Section 13 12 USB device controller initialization to...

Page 422: ...pin modes in registers PINSELn and PINMODEn see Section 9 5 Remark UART receive pins should not have pull down resistors enabled 6 Interrupts To enable UART interrupts set bit DLAB 0 in register U0 2...

Page 423: ...423 of 792 NXP Semiconductors UM10237 Chapter 16 LPC24XX Universal Asynchronous Receiver Transmitter 4 Register description Each UART contains registers as shown in Table 16 377 The Divisor Latch Acc...

Page 424: ...THR DLAB 0 Transmit Holding Register 8 bit Write Data WO NA U0THR 0xE000 C000 U2THR 0xE007 8000 U3THR 0xE007 C000 DLL DLAB 1 Divisor Latch LSB 8 bit Data R W 0x01 U0DLL 0xE000 C000 U2DLL 0xE007 8000...

Page 425: ...bits content LSR Line Status Register RX FIFO Error TEMT THRE BI FE PE OE DR RO 0x60 U0LSR 0xE000 C014 U2LSR 0xE007 8014 U3LSR 0xE007 C014 SCR Scratch Pad Register 8 bit Data R W 0x00 U0SCR 0xE000 C0...

Page 426: ...X FIFO and can be written via the bus interface The LSB represents the first bit to transmit The Divisor Latch Access Bit DLAB in UnLCR must be zero in order to access the UnTHR The UnTHR is always Wr...

Page 427: ...etermines the baud rate of the UARTn 0x00 Table 382 UARTn Interrupt Enable Register U0IER address 0xE000 C004 U2IER 0xE007 8004 U3IER 0xE007 C004 when DLAB 0 bit description Bit Symbol Value Descripti...

Page 428: ...t priority interrupt and is set whenever any one of four error conditions occur on the UARTn Rx input overrun error OE parity error PE framing error FE and break interrupt BI The UARTn Rx error condit...

Page 429: ...014 U3LSR 0xE007 C014 Read Only 3 For details see Section 16 16 4 1 UARTn Receiver Buffer Register U0RBR 0xE000 C000 U2RBR 0xE007 8000 U3RBR 0xE007 C000 when DLAB 0 Read Only 4 For details see Section...

Page 430: ...Table 385 UARTn FIFO Control Register U0FCR address 0xE000 C008 U2FCR 0xE007 8008 U3FCR 0xE007 C008 Write Only bit description Bit Symbol Value Description Reset Value 0 FIFO Enable 0 UARTn FIFOs are...

Page 431: ...it will be odd 0 01 Even Parity Number of 1s in the transmitted character and the attached parity bit will be even 10 Forced 1 stick parity 11 Forced 0 stick parity 6 Break Control 0 Disable break tra...

Page 432: ...tate all 0 s for one full character transmission start data parity stop a break interrupt occurs Once the break condition has been detected the receiver goes idle until RXDn goes to marking state all...

Page 433: ...ble writable byte 0x00 Table 389 UARTn Auto baud Control Register U0ACR 0xE000 C020 U2ACR 0xE007 8020 U3ACR 0xE007 C020 bit description Bit Symbol Value Description Reset value 0 Start This bit is aut...

Page 434: ...n The auto baud function can generate two interrupts The UnIIR ABTOInt interrupt will get set if the interrupt is enabled UnIER ABToIntEn is set and the auto baud rate measurement counter overflows Th...

Page 435: ...clock guaranteeing the start bit is stored in the UnRSR 4 During the receipt of the start bit and the character LSB for mode 0 the rate counter will continue incrementing with the pre scaled UARTn inp...

Page 436: ...aud Fig 65 Autobaud a mode 0 and b mode 1 waveform UARTn RX start bit LSB of A or a rate counter A 0x41 or a 0x61 start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity stop U1ACR start 16 cycles 16xbau...

Page 437: ...uipped with this feature UART0 2 3 baudrate can be calculated as n 0 2 3 2 Where PCLK is the peripheral clock U0 2 3DLM and U0 2 3DLL are the standard UART0 2 3 baud rate divider registers and DIVADDV...

Page 438: ...U0 2 3FDR register value does not comply to these two requests then the fractional divider output is undefined If DIVADDVAL is zero then the fractional divider is disabled and the clock will not be di...

Page 439: ...itter Fig 66 Algorithm for setting UART dividers PCLK BR Calculating UART baudrate BR DL est PCLK 16 x BR DLest is an integer DIVADDVAL 0 MULVAL 1 True FR est 1 5 DL est Int PCLK 16 x BR x FR est 1 1...

Page 440: ...s is 115384 This rate has a relative error of 0 16 from the originally specified 115200 4 13 UARTn Transmit Enable Register U0TER 0xE000 C030 U2TER 0xE007 8030 U3TER 0xE007 C030 LPC2400 s UnTER enabl...

Page 441: ...nput source is the APB clock PCLK The main clock is divided down per the divisor specified in the UnDLL and UnDLM registers This divided down clock is a 16x oversample clock NBAUDOUT The interrupt int...

Page 442: ...UM10237 Chapter 16 LPC24XX Universal Asynchronous Receiver Transmitter Fig 67 UART0 2 and 3 block diagram APB INTERFACE UnLCR UnRX DDIS UnLSR UnFCR UnBRG UnTX INTERRUPT PA 2 0 PSEL PSTB PWRITE PD 7 0...

Page 443: ...FIFO 5 Pins Select UART pins and pin modes in registers PINSELn and PINMODEn see Section 9 5 Remark UART receive pins should not have pull down resistors enabled 6 Interrupts To enable UART interrupts...

Page 444: ...peration of the modem interface U1MCR 4 0 the complement value of this signal is stored in U1MSR 7 State change information is stored in U1MSR3 and is a source for a priority level 4 interrupt if enab...

Page 445: ...atch LSB 8 bit Data R W 0x01 0xE001 0000 DLAB 1 U1DLM Divisor Latch MSB 8 bit Data R W 0x00 0xE001 0004 DLAB 1 U1IER Interrupt Enable Register Reserved Enable Autobaud Time Out Interrupt Enable End of...

Page 446: ...erved User manual Rev 02 19 December 2008 446 of 792 NXP Semiconductors UM10237 Chapter 17 LPC24XX Universal Asynchronous Receiver Transmitter 1 Reset Value reflects the data stored in used bits only...

Page 447: ...h Access Bit DLAB in U1LCR must be zero in order to access the U1THR The U1THR is always Write Only 4 3 UART1 Divisor Latch LSB and MSB Registers U1DLL 0xE001 0000 and U1DLM 0xE001 0004 when DLAB 1 Th...

Page 448: ...16 256 U1DLM U1DLL Table 401 UART1 Interrupt Enable Register U1IER address 0xE001 0004 when DLAB 0 bit description Bit Symbol Value Description Reset Value 0 RBR Interrupt Enable 0 enables the Receiv...

Page 449: ...d by clearing the U1IER 3 bit in the U1IER register In auto cts mode a transition on the CTS1 bit will trigger an interrupt only if both the U1IER 3 and U1IER 7 bits are set 0 0 Disable the CTS interr...

Page 450: ...evel defined in U1FCR7 6 and is reset when the UART1 Rx FIFO depth falls below the trigger level When the RDA interrupt goes active the CPU can read a block of data defined by the trigger level The CT...

Page 451: ...rom occurring at system start up The initialization conditions implement a one character delay minus the stop bit whenever THRE 1 and there have not been at least two characters in the U1THR at one ti...

Page 452: ...or proper UART1 operation Any transition on this bit will automatically clear the UART1 FIFOs 1 RX FIFO Reset 0 No impact on either of UART1 FIFOs 0 1 Writing a logic 1 to U1FCR 1 will clear all bytes...

Page 453: ...lue 0 DTR Control Source for modem output pin DTR This bit reads as 0 when modem loopback mode is active 0 1 RTS Control Source for modem output pin RTS This bit reads as 0 when modem loopback mode is...

Page 454: ...reasserted to a low value once the receiver FIFO has reached the previous trigger level The reassertion of RTS1 signals to the sending UART to continue transmitting data If Auto RTS mode is disabled...

Page 455: ...ed a CTS1 state change does not trigger host interrupts because the device automatically controls its own transmitter Without Auto CTS the transmitter sends any data present in the transmit FIFO and a...

Page 456: ...clears U1LSR 2 Time of parity error detection is dependent on U1FCR 0 Note A parity error is associated with the character at the top of the UART1 RBR FIFO 0 Parity error status is inactive 1 Parity e...

Page 457: ...oaded into the U1RBR This bit is cleared when the U1LSR register is read and there are no subsequent errors in the UART1 FIFO 0 U1RBR contains no UART1 RX errors or U1FCR 0 0 1 UART1 RBR contains at l...

Page 458: ...te Complement of input DCD This bit is connected to U1MCR 3 in modem loopback mode 0 Table 409 UART1 Modem Status Register U1MSR address 0xE001 0018 bit description Bit Symbol Value Description Reset...

Page 459: ...measurement will restart at the next falling edge of the UART1 Rx pin The auto baud function can generate two interrupts The U1IIR ABTOInt interrupt will get set if the interrupt is enabled U1IER ABT...

Page 460: ...beginning of the start bit The rate measuring counter will start counting pclk cycles optionally pre scaled by the fractional baud rate generator 3 During the receipt of the start bit 16 pulses are ge...

Page 461: ...utput clock according to the specified fractional requirements Important If the fractional divider is active DIVADDVAL 0 and DLM 0 the value of the DLL register must be 3 or greater a Mode 0 start bit...

Page 462: ...divider output is undefined If DIVADDVAL is zero then the fractional divider is disabled and the clock will not be divided 4 16 1 Baudrate calculation UART can operate with or without using the Fract...

Page 463: ...itter Fig 71 Algorithm for setting UART dividers PCLK BR Calculating UART baudrate BR DL est PCLK 16 x BR DLest is an integer DIVADDVAL 0 MULVAL 1 True FR est 1 5 DL est Int PCLK 16 x BR x FR est 1 1...

Page 464: ...ive error of 0 16 from the originally specified 115200 4 17 UART1 Transmit Enable Register U1TER 0xE001 0030 In addition to being equipped with full hardware flow control auto cts and auto rts mechani...

Page 465: ...mbles the data to transmit via the serial output pin TXD1 The UART1 Baud Rate Generator block U1BRG generates the timing enables used by the UART1 TX block The U1BRG clock input source is the APB cloc...

Page 466: ...rmation from the U1TX and U1RX is stored in the U1LSR Control information for the U1TX and U1RX is stored in the U1LCR Fig 72 UART1 block diagram APB INTERFACE U1LCR U1RX DDIS U1LSR U1FCR U1BRG U1TX I...

Page 467: ...the VICIntEnable register Table 7 106 6 CAN controller initialization see CANMOD register Section 18 8 1 3 CAN controllers Controller Area Network CAN is the definition of a high performance communic...

Page 468: ...as well as 29 bit identifier Double Receive Buffer and Triple Transmit Buffer Programmable Error Warning Limit and Error Counters with read write access Arbitration Lost Capture and Error Code Captur...

Page 469: ...lock includes interfaces to the following blocks APB Interface Acceptance Filter Vectored Interrupt Controller VIC CAN Transceiver Common Status Registers 6 1 APB Interface Block AIB The APB Interface...

Page 470: ...ID Index field see Section 18 8 9 1 ID index field The received Data Length Code represents the real transmitted Data Length Code which may be greater than 8 depending on transmitting CAN node Neverth...

Page 471: ...e 6 7 Bit Stream Processor BSP The Bit Stream Processor is a sequencer controlling the data stream between the Transmit Buffer Receive Buffers and the CAN Bus It also performs the error detection arbi...

Page 472: ...se the transmission of a CAN message s is initiated by setting Self Reception Request bit SRR in conjunction with the selected Message Buffer bits STB3 STB2 STB1 in the CAN Controller Command register...

Page 473: ...EFF_GRP_sa Extended Frame Group Start Address Register R W 0 0xE003 C010 ENDofTable End of AF Tables register R W 0 0xE003 C014 LUTerrAd LUT Error Address register RO 0 0xE003 C018 LUTerr LUT Error R...

Page 474: ...bytes 5 8 Tx Buffer 1 R W CAN1TDB1 0xE004 403C CAN2TDB1 0xE004 803C CAN1TDB1 0xE004 403C CAN2TDB1 0xE004 803C TFI2 Transmit frame info Tx Buffer 2 R W CAN1TFI2 0xE004 4040 CAN2TFI2 0xE004 8040 CAN1TF...

Page 475: ...t SR Status Status RFS Rx Info and Index Rx Info and Index Rx Info and Index RID Rx Identifier Rx Identifier Rx Identifier RDA Rx Data Rx Data Rx Data RDB Rx Info and Index Rx Info and Index Rx Info a...

Page 476: ...clearing of Reset Mode setting of SM is possible only when Bus Free is detected again 6 The LOM and STM bits can only be written if the RM bit is 1 prior to the write operation 8 2 Command Register C...

Page 477: ...8 6 3 Transmit Buffers TXB 1 1 3 AT Abort Transmission 0 0 0 no action Do not abort the transmission 1 present if not already in progress a pending Transmission Request for the selected Transmit Buffe...

Page 478: ...N2MOD 0xE004 8000 8 3 Global Status Register CAN1GSR 0xE004 x008 CAN2GSR 0xE004 8008 The content of the Global Status Register reflects the status of the CAN Controller This register is read only exce...

Page 479: ...CPU clears the Reset Mode bit Once this is completed the CAN Controller will wait the minimum protocol defined time 128 occurrences of the Bus Free signal counting down the Transmit Error Counter Aft...

Page 480: ...e that a CPU forced content change of the TX Error Counter is possible only if the Reset Mode was entered previously An Error or Bus Status change Status Register an Error Warning or an Error Passive...

Page 481: ...ut of TXB1 was successfully transmitted or aborted indicating that Transmit buffer 1 is available and the TIE1 bit in CANxIER is 1 0 0 2 EI 0 reset 1 set Error Warning Interrupt This bit is set on eve...

Page 482: ...bit is set when the TBS2 bit in CANxSR goes from 0 to 1 whenever a message out of TXB2 was successfully transmitted or aborted indicating that Transmit buffer 2 is available and the TIE2 bit in CANxIE...

Page 483: ...a Length Code 01010 Data Field 01000 CRC Sequence 11000 CRC Delimiter 11001 Acknowledge Slot 11011 Acknowledge Delimiter 11010 End of Frame 10010 Intermission 10001 Active Error Flag 10110 Passive Err...

Page 484: ...at time the current bit position of the Bit Stream Processor is captured into the Arbitration Lost Capture Register The content within this register is fixed until the user application has read out it...

Page 485: ...respective interrupt 0 X 3 DOIE Data Overrun Interrupt Enable If the Data Overrun Status bit is set see Status Register the CAN Controller requests the respective interrupt 0 X 4 WUIE Wake Up Interrup...

Page 486: ...ster CAN1BTR address 0xE004 4014 CAN2BTR address 0xE004 8014 bit description Bit Symbol Value Function Reset Value RM Set 9 0 BRP Baud Rate Prescaler The APB clock is divided by this value plus one to...

Page 487: ...ng Limit register CAN1EWL address 0xE004 4018 CAN2EWL address 0xE004 8018 bit description Bit Symbol Function Reset Value RM Set 7 0 EWL During CAN operation this value is compared to both the Tx and...

Page 488: ...l to the RS bit in the GSR 1 0 13 TS2 Transmit Status 2 1 0 0 idle There is no transmission from Tx Buffer 2 1 transmit The CAN Controller is transmitting a message from Tx Buffer 2 14 ES Error Status...

Page 489: ...is 0 this value is the zero based number of the Lookup Table RAM entry at which the Acceptance Filter matched the received Identifier Disabled entries in the Standard tables are included in this numb...

Page 490: ...register contains the first 1 4 Data bytes of the current received message It is read only in normal operation but can be written for testing purposes if the RM bit in CANMOD is 1 See Table 18 417 for...

Page 491: ...scribes the Frame Format the Data Length and whether it is a Remote or Data Frame In addition a TX Priority register allows the definition of a certain priority for each transmit message Depending on...

Page 492: ...ansmission with the same identifier simultaneously For reasons of compatibility no DLC 8 should be used If a value greater than 8 is selected 8 bytes are transmitted in the data frame with the Data Le...

Page 493: ...ber of transferred data bytes The first bit transmitted is the most significant bit of TX Data Byte 1 Table 434 Transfer Identifier Register CAN1TID 1 2 3 address 0xE004 40 34 44 54 CAN2TID 1 2 3 addr...

Page 494: ...this countdown by reading the Tx Error Counter When this countdown is complete the CAN Controller clears BS and ES in CANxSR and sets EI in CANxSR if EIE in IER is 1 The Tx and Rx error counters can...

Page 495: ...right to send their messages based on the value of their CAN Identifier TID If TPM is 1 they contend based on the PRIO fields in bits 7 0 of their CANxTFS registers In both cases the smallest binary...

Page 496: ...2 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined NA 8 RB1 When 1 a received message is available in the CAN1 controller same as RBS in...

Page 497: ...access is allowed in all Acceptance Filter Modes 12 1 Acceptance filter Off mode The Acceptance Filter Off Mode is typically used during initialization During this mode an unconditional access to all...

Page 498: ...ook up table RAM Four 12 bit section configuration registers SFF_sa SFF_GRP_sa EFF_sa EFF_GRP_sa are used to define the boundaries of the different identifier sections in the ID Look up Table Memory T...

Page 499: ...bits in Standard entries provide a means to turn response to particular CAN Identifiers or ranges of Identifiers on and off dynamically When the Acceptance Filter function is enabled only the disable...

Page 500: ...reads the Controller number the size of the Identifier and the Identifier itself from the Controller It then proceeds to search its RAM to determine whether the message should be received or ignored...

Page 501: ...e section configuration registers allow the use of a 512x32 2 kB look up table RAM The whole ID Look up Table RAM is only word accessible All five section configuration registers contain APB addresses...

Page 502: ...mpatibility with possible future devices write zeroes in bits 31 11 and 1 0 of this register If the eFCAN bit in the AFMR is 1 this value also indicates the size of the table of Standard IDs which the...

Page 503: ...cribed below The largest value that should be written to this register is 0x800 when both Extended Tables are empty and the last word address 0x7FC in AF Lookup Table RAM is used For compatibility wit...

Page 504: ...ctive AF table For compatibility with possible future devices please write zeroes in bits 31 12 and 1 0 of this register If the eFCAN bit in the AFMR is 0 the largest value that should be written to t...

Page 505: ...th the other CAN interrupts from the CAN controllers to produce the request for a VIC interrupt channel 0 31 1 Reserved user software should not write ones to reserved bits The value read from a reser...

Page 506: ...nce filter starts in the following order 1 FullCAN Standard Frame Format Identifier Section 2 Explicit Standard Frame Format Identifier Section 3 Group of Standard Frame Format Identifier Section 4 Ex...

Page 507: ...0x5B to 0x5F will find a match in this Group Identifier Section This way the user can switch dynamically between different filter modes for same identifiers 17 FullCAN mode The FullCAN mode is based o...

Page 508: ...to be done times two SFF_sa must be rounded up to a multiple of 4 if necessary The EndOfTable register must be less than or equal to 0x800 minus 6 times the SFF_sa value to allow 12 bytes of message...

Page 509: ...setting SEM 1 0 11 Before reading a message object the CPU should read SEM 1 0 to determine the current state of the Acceptance Filter activity therein If SEM 1 0 01 then the Acceptance Filter is cur...

Page 510: ...18 LPC24XX CAN controllers CAN1 2 Fig 82 Semaphore procedure for reading an auto stored message read 1st word SEM 01 SEM 11 clear SEM write back 1 st word read 2nd and 3rd words read 1st word SEM 00 S...

Page 511: ...ation Software has to solve the following 1 Index Object number calculation based on the bit position in the FCANIC Interrupt Register for more than one pending interrupt 2 Interrupt priority handling...

Page 512: ...ullCAN section example of the ID look up table 0 FullCAN Explicit Standard Frame Format Identifier Section 11 bit CAN ID SCC 0 Message disable bit Message disable bit Index 0 1 Index 2 3 Index 4 5 Ind...

Page 513: ...erted already During the first write access from the data storage of a FullCAN message object the Message Lost bit of a FullCAN object MsgLostx gets asserted if the interrupt pending bit is set alread...

Page 514: ...ct IntPndx is already asserted the Message Lost Signal gets asserted Fig 85 Normal case no messages lost 01 11 IntPndx semaphore bits look up table access 00 MsgLostx message handler access ARM proces...

Page 515: ...errupt bit gets set for a second time with the 2nd Object write 17 3 4 Scenario 3 1 Message gets overwritten indicated by Semaphore bits and Message Lost This scenario is a sub case to Scenario 3 in w...

Page 516: ...e lost message is indicated by Message Lost Fig 88 Message overwritten indicated by semaphore bits and message lost 01 11 01 11 00 00 1st Object write 2nd Object write 2nd Object read Interrupt Servic...

Page 517: ...Object read clears the pending Interrupt The 3rd Object write clears the Message Lost bit Every write ID SEM clears Message Lost bit if no pending Interrupt of that object is set Fig 89 Message overwr...

Page 518: ...f a section not being used the start address has to be set onto the value of the next section start address 18 3 Example 3 more than one but not all sections are used If the SFF group is not used the...

Page 519: ...ntains the decimal number of words and entries shown in the next two columns and the ID Index field of the CANRFS register can return the decimal values shown in the column ID Indexes for CAN messages...

Page 520: ...0000 b explicit SFF table lower_boundary 3 4 upper_boundary lower_boundary 3 lower_boundary 3 5 upper_boundary 6 upper_boundary 0 1 3 2 0 1 2 3 22 23 24 25 26 d 22 23 25 24 2 6 34 d 35 d 36 d 38 d 39...

Page 521: ...the upper and lower boundary identifier To provide memory space for four Groups of Standard Frame Format identifiers the EFF_sa register value is set to 0x20 The identifier group with the Index 9 of...

Page 522: ...Standard Frame Format Identifier Section SFF_GRP_sa 0x10 SFF_sa 0x00 2 0 SCC 3 0 SCC Disabled 7 8 0 SCC Disabled 9 Disabled 9 1 SCC 1 SCC Message disable bit Message disable bit 12 SCC ENDofTable 0x40...

Page 523: ...alue is set to 0x10 The identifier with the Index 1 of this section is not used and therefore disabled Explicit standard frame format identifier section 11 bit CAN ID The start address of the Explicit...

Page 524: ...eneral rules for programming the Look up Table apply Fig 93 ID Look up table configuration example FullCAN activated and enabled 15 0 SCC 0 14 0 SCC 0 FullCAN Explicit Standard Frame Format Identifier...

Page 525: ...nized as a sorted list or table with an increasing order of the Source CAN Channel SCC in conjunction with the CAN Identifier there is no exception for disabled identifiers The upper and lower bound i...

Page 526: ...ters and slaves being connected to a given bus Only a single master and a single slave can communicate on the interface during a given data transfer During a data transfer the master always sends 8 to...

Page 527: ...and begin the transfer The transfer ends when the last clock cycle of the transfer is complete Fig 94 SPI data transfer format CPHA 0 and CPHA 1 MISO CPHA 1 MOSI CPHA 1 Cycle CPHA 1 CPHA 1 MISO CPHA...

Page 528: ...eption of the serial data Data is written to the SPI data register for the transmit case There is no buffer between the data register and the internal shift register A write to the data register goes...

Page 529: ...from the SPI data register optional 6 Go to step 2 if more data is required to transmit Note A read or write of the SPI data register is required in order to clear the SPIF status bit Therefore at le...

Page 530: ...ri stated SSEL Input Slave Select The SPI slave select signal is an active low signal that indicates which slave is currently selected to participate in a data transfer Each slave has its own unique s...

Page 531: ...ster R W 0x00 0xE002 0008 S0SPCCR SPI Clock Counter Register This register controls the frequency of a master s SCK0 R W 0x00 0xE002 000C S0SPINT SPI Interrupt Flag This register contains the interrup...

Page 532: ...000 1000 8 bits per transfer 1001 9 bits per transfer 1010 10 bits per transfer 1011 11 bits per transfer 1100 12 bits per transfer 1101 13 bits per transfer 1110 14 bits per transfer 1111 15 bits per...

Page 533: ...0010 Note that the bits in this register are intended for functional verification only This register should not be used for normal operation 5 ROVR Read overrun When 1 this bit indicates that a read o...

Page 534: ...write ones to reserved bits The value read from a reserved bit is not defined NA 7 1 Test SPI test mode When 0 the SPI operates normally When 1 SCK will always be on independent of master mode select...

Page 535: ...Semiconductors UM10237 Chapter 19 LPC24XX SPI Fig 95 SPI block diagram MOSI_IN MOSI_OUT MISO_IN MISO_OUT OUTPUT ENABLE LOGIC SPI REGISTER INTERFACE SPI Interrupt APB Bus SPI SHIFT REGISTER SCK_OUT_EN...

Page 536: ...5 Initialization see Table 20 471 and Table 20 472 2 Features Compatible with Motorola SPI 4 wire TI SSI and National Semiconductor Microwire buses Synchronous Serial Communication Master or slave ope...

Page 537: ...ial data to shortly after the end of serial data to signify a data transfer as appropriate for the selected bus and mode When the SSPn is a bus slave this signal qualifies the presence of data from th...

Page 538: ...r on the falling edge of each CLK The received data is transferred from the serial shifter to the receive FIFO on the first rising edge of CLK after the LSB has been latched 5 2 SPI frame format The S...

Page 539: ...idle periods The CLK signal is forced LOW SSEL is forced HIGH The transmit MOSI MISO pad is in high impedance If the SSP is enabled and there is valid data within the transmit FIFO the start of trans...

Page 540: ...98 which covers both single and continuous transfers In this configuration during idle periods The CLK signal is forced LOW SSEL is forced HIGH The transmit MOSI MISO pad is in high impedance If the S...

Page 541: ...SCK signal In the case of a single word transmission after all bits of the data word are transferred the SSEL line is returned to its idle HIGH state one SCK period after the last bit has been capture...

Page 542: ...ime the SCK is enabled with a falling edge transition Data is then captured on the rising edges and propagated on the falling edges of the SCK signal After all bits have been transferred in the case o...

Page 543: ...or the duration of the frame transmission The SI pin remains tristated during this transmission The off chip serial slave device latches each control bit into its serial shifter on the rising edge of...

Page 544: ...20 103 illustrates these setup and hold time requirements With respect to the SK rising edge on which the first bit of receive data is to be sampled by the SSP slave CS must have a setup of at least t...

Page 545: ...CR0 0xE003 0000 CR1 Control Register 1 Selects master slave and other modes R W 0 SSP0CR1 0xE006 8004 SSP1CR1 0xE003 0004 DR Data Register Writes fill the transmit FIFO and reads empty the receive FIF...

Page 546: ...sfer 1100 13 bit transfer 1101 14 bit transfer 1110 15 bit transfer 1111 16 bit transfer 5 4 FRF Frame Format 00 00 SPI 01 TI 10 Microwire 11 This combination is not supported and should not be used 6...

Page 547: ...line and receiving SCLK MOSI and SSEL lines 3 SOD Slave Output Disable This bit is relevant only in slave mode MS 1 If it is 1 this blocks this SSP controller from driving the transmit data line MISO...

Page 548: ...he four possible interrupt conditions in the SSP controller are enabled Note that ARM uses the word masked in the opposite sense from classic computer terminology in which masked meant disabled ARM us...

Page 549: ...frame data is overwritten by the new frame data when this occurs 0 1 RTIM Software should set this bit to enable interrupt when a Receive Timeout condition occurs A Receive Timeout occurs when the Rx...

Page 550: ...errupt is enabled 0 2 RXMIS This bit is 1 if the Rx FIFO is at least half full and this interrupt is enabled 0 3 TXMIS This bit is 1 if the Tx FIFO is at least half empty and this interrupt is enabled...

Page 551: ...dia memory card such as the clock generation unit power management control command and data transfer The APB interface accesses the MCI adapter registers and generates interrupt and DMA request signal...

Page 552: ...g to their function Read Only Memory ROM cards containing pre programmed data Read Write R W cards used for mass storage Input Output I O cards used for communication The multimedia card system transf...

Page 553: ...21 106 shows a simplified block diagram of the MCI adapter The MCI adapter is a multimedia secure digital memory card bus master that provides an interface to a multimedia card stack or to a secure d...

Page 554: ...ting voltage A device driver is used to ensure that the PrimeCell MCI remains in the power up phase until the external power supply reaches the operating voltage The clock management logic generates a...

Page 555: ...path subunit When CmdPend is detected the CPSM moves to the SEND state This enables the data counter to trigger the stop command transmission Figure 21 108 shows the MCI command transfer Fig 107 Comma...

Page 556: ...tatus The command register contains the command index six bits sent to a card and the command type These determine whether the command requires a response and whether the response is 48 or 136 bits lo...

Page 557: ...l four data signals MCIDAT 3 0 If the wide bus mode is not enabled only one bit per clock cycle is transferred over MCIDAT0 Depending on the transfer direction send or receive the Data Path State Mach...

Page 558: ...ta control register the data transfer mode can be either block or stream In block mode when the data block counter reaches zero the DPSM waits until it receives the CRC code If the received code match...

Page 559: ...waits for the CRC status flag If it does not receive a positive CRC status it moves to the IDLE state and sets the CRC fail status flag If it receives a positive CRC status it moves to the WAIT_S stat...

Page 560: ...is either sent to a card or received from a card While not being transferred MCIDAT 3 0 are in the HI Z state Data on these signals is synchronous to the rising edge of the clock period If standard b...

Page 561: ...in the MCI clock domain MCLK are resynchronized Depending on TxActive and RxActive the FIFO can be disabled transmit enabled or receive enabled TxActive and RxActive are driven by the data path subuni...

Page 562: ...he receive FIFO control logic asserts RxWrDone that then deasserts the write enable signal On the read side the content of the FIFO word pointed to by the current value of the read pointer is driven o...

Page 563: ...lfFull Set to HIGH when 8 or more receive FIFO words contain valid data This flag can be used as a DMA request RxDataAvlbl Set to HIGH when the receive FIFO is not empty This flag is the inverse of th...

Page 564: ...HIGH The card bus outlets are disabled during both phases Note After a data write data cannot be written to this register for three MCLK clock periods plus two PCLK clock periods 6 2 Clock Control Re...

Page 565: ...ts The command index is sent to a card as part of a command message The command type bits control the Command Path State Machine CPSM Writing 1 to the enable bit starts the command send operation whil...

Page 566: ...ws the bit assignment of the MCIResponse0 3 registers Table 494 Command register MCICommand address 0xE008 C00C bit description Bit Symbol Description Reset Value 5 0 CmdIndex Command index 0 6 Respon...

Page 567: ...ded into the data counter when data transfer starts Table 21 500 shows the bit assignment of the MCIDataLength register For a block data transfer the value in the data length register must be a multip...

Page 568: ...the data length register see Section 21 6 8 Data Length Register MCIDataLength 0xE008 C028 when the DPSM moves from the IDLE state to the WAIT_R or WAIT_S state As data is transferred the counter dec...

Page 569: ...software should not write ones to reserved bits The value read from a reserved bit is not defined NA Table 504 Status register MCIStatus address 0xE008 C034 bit description Bit Symbol Description Rese...

Page 570: ...ster MCIStatus address 0xE008 C034 bit description Bit Symbol Description Reset Value Table 505 Clear register MCIClear address 0xE008 C038 bit description Bit Symbol Description Reset Value 0 CmdCrcF...

Page 571: ...ws the bit assignment of the MCIFIFO register 8 Mask8 Mask DataEnd flag 0 9 Mask9 Mask StartBitErr flag 0 10 Mask10 Mask DataBlockEnd flag 0 11 Mask11 Mask CmdActive flag 0 12 Mask12 Mask TxActive fla...

Page 572: ...en simultaneously transmitting masters without corruption of serial data on the bus Programmable clock to allow adjustment of I2C transfer rates Bidirectional data transfer between masters and slaves...

Page 573: ...receiver mode slave transmitter mode and slave receiver mode The three I2C interfaces are identical except for the pin I O characteristics I2C0 complies with entire I2C specification supporting the a...

Page 574: ...device 7 bits and the data direction bit In this mode the data direction bit R W should be 0 which means Write The first byte transmitted contains the slave address and Write bit Data is transmitted 8...

Page 575: ...an acknowledge bit has been received the SI bit is set and the Status Register will show the status code For master mode the possible status codes are 0x40 0x48 or 0x38 For slave mode the possible st...

Page 576: ...rs slave receiver mode If the direction bit is 1 R it enters slave transmitter mode After the address and direction bit have been received the SI bit is set and a valid status code can be read from th...

Page 577: ...bus is free before the master mode is entered so that a possible slave action is not interrupted If bus arbitration is lost in the master mode the I2C interface switches to the slave mode immediately...

Page 578: ...al interface block diagram APB BUS STATUS REGISTER CONTROL REGISTER SCL DUTY CYCLE REGISTERS ADDRESS REGISTER COMPARATOR SHIFT REGISTER 8 8 ACK I2ADR I2DAT 8 16 BIT COUNTER ARBITRATION SYNC LOGIC SERI...

Page 579: ...ster transmitter to slave receiver is made with the correct data in I2DAT 7 5 Arbitration and synchronization logic In the master transmitter mode the arbitration logic checks that every transmitted l...

Page 580: ...and duty cycle is programmable via the I2C Clock Control Registers See the description of the I2CSCLL and I2CSCLH registers for details The output clock pulses have a duty cycle as programmed unless t...

Page 581: ...ed by eight address locations Eight bytes of code is sufficient for most of the service routines see the software example in this section 8 Register description Each I2C interface contains 7 registers...

Page 582: ...ter mode I2SCLH SCH Duty Cycle Register High Half Word Determines the high time of the I2C clock R W 0x04 I2C0SCLH 0xE001 C010 I2C1SCLH 0xE005 C010 I2C2SCLH 0xE008 0010 I2SCLL SCL Duty Cycle Register...

Page 583: ...omatically In slave mode setting this bit can recover from an error condition In this case no STOP condition is transmitted to the bus The hardware behaves as if a STOP condition has been received and...

Page 584: ...tus register is Read Only The three least significant bits are always 0 Taken as a byte the status register contents represent a status code There are 26 possible status codes When the status code is...

Page 585: ...Register I2C 0 1 2 SCLL 0xE001 C014 0xE005 C014 0xE008 0014 8 8 Selecting the appropriate I2C data rate and duty cycle Software must set values for the registers I2SCLH and I2SCLL to select the approp...

Page 586: ...L and I2SCLH values 9 Details of I2C operating modes The four operating modes are Master Transmitter Master Receiver Slave Receiver Slave Transmitter Data transfers in each mode of operation are shown...

Page 587: ...ing master of the bus In other words if AA is reset the I2C interface cannot enter a slave mode STA STO and SI must be reset The master transmitter mode may now be entered by setting the STA bit The I...

Page 588: ...initiate the slave receiver mode I2ADR and I2CON must be loaded as follows The upper 7 bits are the address to which the I2C block will respond when addressed by a master If the LSB GC is set the I2C...

Page 589: ...nsfer the I2C block will return a not acknowledge logic 1 to SDA after the next received data byte While AA is reset the I2C block does not respond to its own slave address or a general call address H...

Page 590: ...her Master continues A other Master continues 20H 08H 18H 28H 30H 10H 68H 78H B0H 38H 38H arbitration lost in Slave address or Data byte Not Acknowledge received after a Data byte Not Acknowledge rece...

Page 591: ...es other Master continues A other Master continues 48H 40H 58H 10H 68H 78H B0H 38H 38H arbitration lost in Slave address or Acknowledge bit Not Acknowledge received after the Slave address next transf...

Page 592: ...as Master and addressed as Slave last data byte received is Not acknowledged arbitration lost as Master and addressed as Slave by General Call reception of the own Slave address and one or more Data b...

Page 593: ...is in the master mode see state 0xB0 If the AA bit is reset during a transfer the I2C block will transmit the last byte of the transfer and enter state 0xC0 or 0xC8 The I2C block is switched to the n...

Page 594: ...e will be transmitted ACK bit will be received No I2DAT action or 1 0 0 X Repeated START will be transmitted No I2DAT action or 0 1 0 X STOP condition will be transmitted STO flag will be reset No I2D...

Page 595: ...as been transmitted ACK has been received No I2DAT action or 0 0 0 0 Data byte will be received NOT ACK bit will be returned No I2DAT action 0 0 0 1 Data byte will be received ACK bit will be returned...

Page 596: ...ata byte will be received and NOT ACK will be returned No I2DAT action X 0 0 1 Data byte will be received and ACK will be returned 0x80 Previously addressed with own SLV address DATA has been received...

Page 597: ...ADR 0 logic 1 A START condition will be transmitted when the bus becomes free 0xA0 A STOP condition or repeated START condition has been received while still addressed as SLV REC or SLV TRX No STDAT a...

Page 598: ...ion or 0 0 0 0 Switched to not addressed SLV mode no recognition of own SLA or General call address No I2DAT action or 0 0 0 1 Switched to not addressed SLV mode Own SLA will be recognized General cal...

Page 599: ...9 5 2 I2STAT 0x00 This status code indicates that a bus error has occurred during an I2C serial transfer A bus error is caused when a START or STOP condition occurs at an illegal position in the forma...

Page 600: ...er modes see Figure 22 118 Loss of arbitration is indicated by the following states in I2STAT 0x38 0x68 0x78 and 0xB0 see Figure 22 120 and Figure 22 121 If the STA flag in I2CON is set by the routine...

Page 601: ...e the SDA line is pulled LOW while the I2C bus is considered free The I2C hardware attempts to generate a START condition after every two additional clock pulses on the SCL line When the SDA line is e...

Page 602: ...ssion and reception The initialization routine performs the following functions I2ADR is loaded with the part s own slave address and the general call bit GC The I2C interrupt enable and interrupt pri...

Page 603: ...aken that the those states can never occur In an application it may be desirable to implement some kind of timeout during I2C operations in order to trap an inoperative bus or a lost service routine 1...

Page 604: ...I2CONSET to set the STO and AA bits 2 Write 0x08 to I2CONCLR to clear the SI flag 3 Exit 10 6 Master states State 08 and State 10 are for both Master Transmit and Master Receive modes The R W bit deci...

Page 605: ...n transmitted NOT ACK has been received A Stop condition will be transmitted 1 Write 0x14 to I2CONSET to set the STO and AA bits 2 Write 0x08 to I2CONCLR to clear the SI flag 3 Exit 10 7 3 State 0x28...

Page 606: ...lear the SI flag 3 Exit 10 8 2 State 0x48 Slave Address Read has been transmitted NOT ACK has been received A Stop condition will be transmitted 1 Write 0x14 to I2CONSET to set the STO and AA bits 2 W...

Page 607: ...e has been received ACK has been returned Data will be received and ACK will be returned STA is set to restart Master mode after the bus is free again 1 Write 0x24 to I2CONSET to set the STA and AA bi...

Page 608: ...en received and NOT ACK has been returned Received data will not be saved Not addressed Slave mode is entered 1 Write 0x04 to I2CONSET to set the AA bit 2 Write 0x08 to I2CONCLR to clear the SI flag 3...

Page 609: ...ter Own Slave Address Read has been received ACK has been returned Data will be transmitted ACK bit will be received STA is set to restart Master mode after the bus is free again 1 Load I2DAT from Sla...

Page 610: ...NXP Semiconductors UM10237 Chapter 22 LPC24XX I2C interfaces I2C0 1 2 3 Exit 10 10 5 State 0xC8 The last data byte has been transmitted ACK has been received Not addressed Slave mode is entered 1 Writ...

Page 611: ...o and stereo audio data supported The sampling frequency can range in practice from 16 96 kHz 16 22 05 32 44 1 48 96 kHz for audio applications Word Select period in master mode is configurable separa...

Page 612: ...criptions Pin Name Type Description I2SRX_CLK Input Output Receive Clock A clock signal used to synchronize the transfer of data on the receive channel It is driven by the master and received by the s...

Page 613: ...ECEIVER SLAVE SCK serial clock WS word select SD serial data Table 531 Summary of I2S registers Name Description Access Reset Value 1 Address I2SDAO Digital Audio Output Register Contains control bits...

Page 614: ...lue to divide pclk by in order to produce the transmit bit clock R W 0xE008 8020 I2SRXRATE Receive bit rate divider This register determines the I2S receive bit rate by specifying the value to divide...

Page 615: ...his setting 11 32 bit data 2 mono When one data is of monaural format When zero the data is in stereo format 0 3 stop Disables accesses on FIFOs places the transmit channel in mute mode 0 4 reset Asyn...

Page 616: ...ined NA Table 536 Status Feedback register I2SSTATE address 0xE008 8010 bit description Bit Symbol Description Reset Value Table 537 DMA Configuration register 1 I2SDMA1 address 0xE008 8014 bit descri...

Page 617: ...smitted When mono is false two successive data words are respectively left and right data Table 539 Interrupt Request Control register I2SIRQ address 0xE008 801C bit description Bit Symbol Description...

Page 618: ...until sufficient data has been written in the transmit FIFO Note that when stopped data output is muted All data accesses to FIFO s are 32 bits Figure 23 128 shows the possible data sequences A data...

Page 619: ...h_dma1 rx_level dmareq_tx_2 tx_depth_dma2 tx_level dmareq_rx_2 rx_depth_dma2 rx_level irq_tx tx_depth_irq tx_level irq_rx rx_depth_irq rx_level Table 543 DMA and interrupt request generation System Si...

Page 620: ...I2S interface Fig 128 FIFO contents for various I2S modes LEFT 1 7 0 RIGHT 1 7 0 LEFT 7 0 RIGHT 7 0 Stereo 8 bit data mode N 3 7 0 N 2 7 0 N 1 7 0 N 7 0 Mono 8 bit data mode N 1 15 0 N 15 0 Mono 16 bi...

Page 621: ...A minimum of two Capture inputs and two Match outputs are pinned out for all four timers with a choice of several pins for each Timer 1 brings out a third Match output while Timers 2 and 3 bring out...

Page 622: ...nter contains the registers shown in Table 24 546 Reset Value refers to the data stored in used bits only it does not include reserved bits content More detailed descriptions follow Table 545 Timer Co...

Page 623: ...ounter which is incremented to the value stored in PR When the value in PR is reached the TC is incremented and the PC is cleared The PC is observable and controllable through the bus interface R W 0...

Page 624: ...there is an event on the CAPn 1 pins CAP0 1 CAP1 1 CAP2 1 CAP3 1 inputs RO 0 T0CR1 0xE000 4030 T1CR1 0xE000 8030 T2CR1 0xE007 0030 T3CR1 0xE007 4030 EMR External Match Register The EMR controls the ex...

Page 625: ...h low levels on the same CAP input in this case can not be shorter than 1 2 PCLK Table 548 Timer Control Register TCR TIMERn TnTCR addresses 0xE000 4004 0xE000 8004 0xE007 0004 0xE007 4004 bit descrip...

Page 626: ...ented on every PCLK When it reaches the value stored in the Prescale register the Timer Counter is incremented and the Prescale Counter is reset on the next PCLK This causes the Timer Counter to incre...

Page 627: ...re disabled 3 MR1I 1 Interrupt on MR1 an interrupt is generated when MR1 matches the value in the TC 0 0 This interrupt is disabled 4 MR1R 1 Reset on MR1 the TC will be reset if MR1 matches it 0 0 Fea...

Page 628: ...he CTCR the 3 bits for that input in this register should be programmed as 000 but capture and or interrupt can be selected for the other 3 CAP inputs Table 551 Capture Control Register T 0 1 2 3 CCR...

Page 629: ...go low go high or do nothing depending on bits 9 8 of this register This bit can be driven onto a MATn 0 pin in a positive logic manner 0 low 1 high 0 3 EM3 External Match 3 When a match occurs betwe...

Page 630: ...igure 24 130 shows a timer configured to stop and generate an interrupt on match The prescaler is again set to 2 and the match register set to 6 In the next clock after the timer reaches the match val...

Page 631: ...CONTROL REGISTER PRESCALE REGISTER PRESCALE COUNTER PCLK enable CAPTURE REGISTER 3 CAPTURE REGISTER 2 CAPTURE REGISTER 1 CAPTURE REGISTER 0 MATCH REGISTER 3 MATCH REGISTER 2 MATCH REGISTER 1 MATCH REG...

Page 632: ...h optional interrupt generation on match Stop timer on match with optional interrupt generation Reset timer on match with optional interrupt generation Supports single edge controlled and or double ed...

Page 633: ...ter controls the PWM edge position Additional single edge controlled PWM outputs require only one match register each since the repetition rate is the same for all PWM outputs Multiple single edge con...

Page 634: ...LOAD ENABLE LOAD ENABLE REGISTER CLEAR Match0 SHADOW REGISTER 1 LOAD ENABLE MATCH CONTROL REGISTER INTERRUPT REGISTER CONTROL M 6 0 INTERRUPT STOP ON MATCH RESET ON MATCH CAPTURE 1 0 CAPTURE CONTROL...

Page 635: ...ted at the same time clear takes precedence This can occur when the set and clear match values are the same as in or when the set or clear value equals 0 and the other value equals the PWM rate 5 If a...

Page 636: ...elate to waveform outputs is shown in Figure 25 133 PWM output logic is shown in Figure 25 132 that allows selection of either single or double edge controlled PWM outputs via the muxes controlled by...

Page 637: ...and reset inputs for PWM flip flops PWM Channel Single Edge PWM PWMSELn 0 Double Edge PWM PWMSELn 1 Set by Reset by Set by Reset by 1 Match 0 Match 1 Match 0 1 Match 1 1 2 Match 0 Match 2 Match 1 Mat...

Page 638: ...and PC and or generate an interrupt when it matches the TC In addition a match between this value and the TC sets any PWM output that is in single edge mode and sets PWM1 if it s in double edge mode...

Page 639: ...MCR to reset the TC stop both the TC and PC and or generate an interrupt when it matches the TC In addition a match between this value and the TC clears PWM6 in either edge mode R W 0 0xE001 4048 PWM0...

Page 640: ...tive edge of PCLK The counters remain reset until this bit is returned to zero 0 0 Clear reset 2 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not...

Page 641: ...ode 00 Timer Mode the TC is incremented when the Prescale Counter matches the Prescale register 01 Counter Mode the TC is incremented on rising edges of the PCAP input selected by bits 3 2 10 Counter...

Page 642: ...es the PWxMTC 0 0 This feature is disabled 9 PWMMR3I 1 Interrupt on PWMMR3 an interrupt is generated when PWMMR3 matches the value in the PWMTC 0 0 This interrupt is disabled 10 PWMMR3R 1 Reset on PWM...

Page 643: ...e PWMTC 0 0 This feature is disabled 18 PWMMR6I 1 Interrupt on PWMMR6 an interrupt is generated when PWMMR6 matches the value in the PWMTC 0 0 This interrupt is disabled 19 PWMMR6R 1 Reset on PWMMR6 t...

Page 644: ...and PWM1CCR address 0xE001 8028 bit description Bit Symbol Value Description Reset Value Table 563 PWM Control Registers PWMPCR address 0xE001 404C and PWM1PCR address 0xE001 804C bit description Bit...

Page 645: ...ts for changing the timing would be Write a new value to the PWM Match1 register Write a new value to the PWM Match2 register Write to the PWMLER setting bits 1 and 2 at the same time The altered valu...

Page 646: ...MR5 register update control See bit 0 for details 0 6 Enable PWM Match 6 Latch PWM MR6 register update control See bit 0 for details 0 7 Reserved user software should not write ones to reserved bits T...

Page 647: ...waking up from Power down mode or when the chip has had power removed to all functions except the RTC and Battery RAM Periodic interrupts can be generated from increments of any field of the time regi...

Page 648: ...INTERRUPT ENABLE ALARM MASK REGISTER counter enables CLK1 REFERENCE CLOCK DIVIDER PRESCALER CLK32k strobe COMPARATORS CLOCK GENERATOR ALARM REGISTERS TIME COUNTERS RTC OSCILLATOR MUX Table 565 RTC pin...

Page 649: ...0xE002 4004 CCR 4 Clock Control Register R W NC 0xE002 4008 CIIR 8 Counter Increment Interrupt Register R W NC 0xE002 400C AMR 8 Alarm Mask Register R W NC 0xE002 4010 CTIME0 32 Consolidated Time Regi...

Page 650: ...d event occurs the oscillator wakeup cycle associated with the XTAL1 2 pins is started For details on the RTC based wakeup process see Section 4 3 4 7 Interrupt Wakeup Register INTWAKE 0xE01F C144 on...

Page 651: ...address 0xE002 4000 bit description Bit Symbol Description Reset value 0 RTCCIF When one the Counter Increment Interrupt block generated an interrupt Writing a one to this bit location clears the cou...

Page 652: ...eserved bits The value read from a reserved bit is not defined NA 4 CLKSRC If this bit is 0 the Clock Tick Counter takes its clock from the Prescaler as on earlier devices in the NXP Embedded ARM fami...

Page 653: ...An interrupt is generated on every 128 counts of the Clock Tick Counter At 32 768 kHz this generates an interrupt approximately every 3 9 milliseconds 100 An interrupt is generated on every 256 counts...

Page 654: ...ue 5 0 Seconds Seconds value in the range of 0 to 59 NA 7 6 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined NA 13 8 Minutes Minutes valu...

Page 655: ...er 2 CTIME2 address 0xE002 401C bit description Bit Symbol Description Reset value 11 0 Day of Year Day of year value in the range of 1 to 365 366 for leap years NA 31 12 Reserved user software should...

Page 656: ...fter adjustment by the reference clock divider If the RTC is used VBAT must be connected to either pin VDD 3V3 or an independent power supply external battery Otherwise VBAT should be left floating No...

Page 657: ...to as the Prescaler may be used when the RTC clock source is not supplied by the RTC oscillator but comes from the APB peripheral clock PCLK The Prescaler allows generation of a 32 768 kHz reference...

Page 658: ...s it is an even number of cycles per second may be turned into a 32 kHz reference clock for the RTC The only caveat is that if PREFRAC does not contain a zero then not all of the 32 768 per second clo...

Page 659: ...mple if PREFRAC bit 14 is a one representing the fraction 1 2 then half of the cycles counted by the 13 bit counter need to be longer When there is a 1 in the LSB of the Fraction Counter the logic cau...

Page 660: ...of the chip This allows them to operate while the main chip power has been removed 12 RTC external 32 kHz oscillator component selection The RTC external oscillator circuit is shown in Figure 26 136 S...

Page 661: ...he quality of the crystal compared to the specified one Therefore for an accurate time reference it is advised to use the load capacitors as specified in Table 26 584 that belong to a specific CL The...

Page 662: ...controller within a reasonable amount of time if it enters an erroneous state When enabled the Watchdog will generate a system reset if the user program fails to feed or reload the Watchdog within a p...

Page 663: ...lue of the counter on WDCLK and then synchronize it with the PCLK for reading as the WDTV register by the CPU 4 Register description The Watchdog contains 4 registers as shown in Table 27 585 below 1...

Page 664: ...OD register is not sufficient to enable the Watchdog A valid feed sequence must be completed after setting WDEN before the Watchdog is capable of generating a reset Until then the Watchdog will ignore...

Page 665: ...clock source for the Watchdog timer The possibilities are the Internal RC oscillator IRC the RTC oscillator and the APB peripheral clock pclk The function of bits in WDCLKSEL are shown in Table 27 59...

Page 666: ...ck diagram of the Watchdog is shown below in the Figure 27 137 The synchronization logic PCLK WDCLK is not shown in the block diagram Fig 137 Watchdog block diagram WDTC 32 BIT DOWN COUNTER WDINT WDTO...

Page 667: ...rupts are enabled in the VIC using the VICIntEnable register Section 7 3 4 2 Features 10 bit successive approximation analog to digital converter Input multiplexing among 8 pins Power down mode Measur...

Page 668: ...A D converter is not used in an application then the pins associated with A D inputs can be used as 5V tolerant digital IO pins VREF Reference Voltage Reference This pin provides a voltage reference l...

Page 669: ...tion Access Reset Value 1 Address Table 594 A D Control Register AD0CR address 0xE003 4000 bit description Bit Symbol Value Description Reset Value 7 0 SEL Selects which of the AD0 7 0 pins is are to...

Page 670: ...d user software should not write ones to reserved bits The value read from a reserved bit is not defined NA 26 24 START 000 When the BURST bit is 0 these bits control whether and when an A D conversio...

Page 671: ...ast 256 values without overflow into the CHN field 0 26 24 CHN These bits contain the channel from which the LS bits were converted X 29 27 Unused These bits always read as zeroes They could be used f...

Page 672: ...bit 1 is one completion of a conversion on A D channel 1 will generate an interrupt etc 0x00 8 ADGINTEN When 1 enables the global DONE flag in ADDR to generate an interrupt When 0 only the individual...

Page 673: ...n logic 6 2 Interrupts An interrupt is requested to the Vectored Interrupt Controller VIC when the ADINT bit in the ADSTAT register is 1 The ADINT bit is one when any of the DONE bits of A D channels...

Page 674: ...VSSA must be grounded These pins should not be left floating 4 Register description DACR 0xE006 C000 This read write register includes the digital value to be converted to analog and a bit that trade...

Page 675: ...cause settling time longer than the specified time One or more graph s of load impedance vs settling time will be included in the final data sheet Table 600 D A Converter Register DACR address 0xE006...

Page 676: ...e is executed every time the part is powered on or reset The loader can execute the ISP command handler or the user application code A LOW level after reset at the P2 10 pin is considered as an extern...

Page 677: ...er reset i e the bottom 64 bytes of the boot block are also visible in the memory region starting from the address 0x0000 0000 The reset vector contains a jump instruction to the entry point of the fl...

Page 678: ...eceived the part is initialized and the ISP command handler is invoked For safety reasons an Unlock command is required before executing the commands resulting in Flash erase write operations and the...

Page 679: ...The on chip Flash memory is not accessible during erase write operations When the user application code starts executing the interrupt vectors from the user Flash area are active The user should eith...

Page 680: ...Reinvoke ISP on page 695 2 For details on available ISP commands based on the CRP settings see Section 30 8 Code Read Protection CRP Fig 139 Boot process flowchart WATCHDOG FLAG SET CRP1 2 3ENABLED y...

Page 681: ...size kB Address range 0 4 0X0000 0000 0X0000 0FFF 1 4 0X0000 1000 0X0000 1FFF 2 4 0X0000 2000 0X0000 2FFF 3 4 0X0000 3000 0X0000 3FFF 4 4 0X0000 4000 0X0000 4FFF 5 4 0X0000 5000 0X0000 5FFF 6 4 0X000...

Page 682: ...restrictions Write to RAM command can not access RAM below 0x40000200 Copy RAM to Flash command can not write to Sector 0 Erase command can erase Sector 0 only when all sectors are selected for erase...

Page 683: ...d Go commands Table 603 Code Read Protection hardware software interaction CRP option User Code Valid P2 10 pin at reset JTAG enabled LPC2400 enters ISP mode partial Flash Update in ISP mode No No X Y...

Page 684: ...LID_CODE PARAM_ERROR Description This command is used to unlock Flash Write Erase and Go commands Example U 23130 CR LF unlocks the Flash Write Erase Go commands Table 606 ISP Set Baud Rate command Co...

Page 685: ...smitting 20 UU encoded lines The checksum is generated by adding raw data before UU encoding bytes and is reset after transmitting 20 UU encoded lines The length of any UU encoded line should not exce...

Page 686: ...coded ADDR_ERROR Address not on word boundary ADDR_NOT_MAPPED COUNT_ERROR Byte count is not a multiple of 4 PARAM_ERROR CODE_READ_PROTECTION_ENABLED Description This command is used to read data from...

Page 687: ...his command is used to program the Flash memory The Prepare Sector s for Write Operation command should precede this command The affected sectors are automatically protected again once the copy comman...

Page 688: ...nd only allows erasure of all user sectors when the code read protection is enabled Example E 2 3 CR LF erases the Flash sectors 2 and 3 Table 615 ISP Blank check sector command Command I Input Start...

Page 689: ...dress2 SRC Starting Flash or RAM address of data bytes to be compared This address should be a word boundary Number of Bytes Number of bytes to be compared should be a multiple of 4 Return Code CMD_SU...

Page 690: ...could be called in the following way using C 3 DST_ADDR_ERROR Destination address is not on a correct boundary 4 SRC_ADDR_NOT_MAPPED Source address is not mapped in the memory map Count value is take...

Page 691: ...call could be simplified further by using the symbol definition file feature supported by ARM Linker in ADS ARM Developer Suite You could also call the IAP routine using assembly code The following s...

Page 692: ...cation 10 1 Prepare sector s for write operation This command makes Flash write erase operation a two step process Table 621 IAP Command Summary IAP Command Command Code Described in Prepare sector s...

Page 693: ...nd sector numbers Table 623 IAP Copy RAM to Flash command Command Copy RAM to Flash Input Command code 5110 Param0 DST Destination Flash address where data bytes are to be written This address should...

Page 694: ...command To erase a single sector use the same Start and End sector numbers Table 625 IAP Blank check sector s command Command Blank check sector s Input Command code 5310 Param0 Start Sector Number Pa...

Page 695: ...command Command Compare Input Command code 5610 Param0 DST Starting Flash or RAM address of data bytes to be compared This address should be a word boundary Param1 SRC Starting Flash or RAM address of...

Page 696: ...1 frequency after autobaud handshake Another option is to disable the PLL and select the IRC as the clock source before making this IAP call In this case frequency sent by ISP is ignored and IRC and...

Page 697: ...algorithms The bootloader implemented in LPC2460 70 supports a limited set of commands dedicated to code download and its execution from on chip RAM only UART0 is the sole serial channel the boot loa...

Page 698: ...ng from the address 0x7FFF E000 The serial boot loader is designed to run from this memory area and both the ISP and IAP software use parts of the on chip RAM The RAM usage is described later in this...

Page 699: ...le at the wotsit webpage 4 2 4 ISP flow control A software XON XOFF flow control scheme is used to prevent data loss due to buffer overrun When the data arrives rapidly the ASCII control character DC3...

Page 700: ...wards 4 2 10 RAM used by RealMonitor The RealMonitor uses on chip RAM from 0x4000 0040 to 0x4000 011F The user could use this area if RealMonitor based debug is not required The serial boot loader doe...

Page 701: ...AM Read Memory and Go commands 6 1 Unlock Unlock code 6 2 Set Baud Rate Baud Rate stop bit Table 631 ISP command summary ISP Command Usage Described in Unlock U Unlock Code Table 31 632 Set Baud Rate...

Page 702: ...ber of bytes sent The ISP command handler compares it with the check sum of the received bytes If the check sum matches the ISP command handler responds with OK CR LF to Return Code CMD_SUCCESS INVALI...

Page 703: ...with RESEND CR LF In response the ISP command handler sends the data again Table 636 ISP Write to RAM command Command W Input Start Address RAM address where data bytes are to be written This address...

Page 704: ...be possible to return to the ISP command handler once this command is successfully executed Example G 0 A CR LF branches to address 0x0000 0000 in ARM mode Table 639 ISP Read Part Identification comma...

Page 705: ...address zero After any reset the first 64 bytes are re mapped to the ROM boot sector Example M 1073742336 1073741824 4 CR LF compares 4 bytes from the RAM address 0x4000 0000 to the 4 bytes from the...

Page 706: ...when an undefined command is received The IAP routine resides at 0x7FFF FFF0 location and it is thumb code The IAP function could be called in the following way using C Define the IAP location entry...

Page 707: ...ort_handler 0x7fffffc0 A rm_dataabort_handler 0x7fffffd0 A rm_irqhandler 0x7fffffe0 A rm_irqhandler2 0x7ffffff0 T iap_entry As per the ARM specification The ARM Thumb Procedure Call Standard SWS ESPC...

Page 708: ...ARM REGISTER r1 Table 645 IAP Read Part Identification command Command Read part identification number Input Command code 5410 Parameters None Return Code CMD_SUCCESS Result Result0 Part Identificati...

Page 709: ...ess zero The first 64 bytes can be re mapped to RAM Table 648 Reinvoke ISP Command Compare Input Command code 5710 Return Code None Result None Description This command is used to invoke the bootloade...

Page 710: ...s not mapped in the memory map Count value is taken in to consideration where applicable 5 DST_ADDR_NOT_MAPPED Destination address is not mapped in the memory map Count value is taken in to considerat...

Page 711: ...g the GPDMA Memory to memory memory to peripheral peripheral to memory and peripheral to peripheral transfers Scatter or gather DMA is supported through the use of linked lists This means that the sou...

Page 712: ...ional blocks of the GPDMA It contains the following sections GPDMA functional description System considerations System connectivity Use with memory management unit based systems 4 1 Memory regions acc...

Page 713: ...nk DMA request and response interface Channel logic and channel register bank Interrupt request AHB master interface Channel hardware DMA request priority 4 2 1 AHB Slave Interface All transactions on...

Page 714: ...Setting of protection bits for transfers on each stream 4 2 7 Bus and transfer widths The physical width of the AHB bus is 32 bits Source and destination transfers can be of differing widths and can...

Page 715: ...87 1 15 0 2 31 16 43214321 87658765 Little Little 8 32 1 7 0 2 15 8 3 23 16 4 31 24 21 43 65 87 1 31 0 87654321 Little Little 16 8 1 7 0 1 15 8 2 23 16 2 31 24 21 43 65 87 1 7 0 2 15 8 3 23 16 4 31 24...

Page 716: ...Big 8 32 1 31 24 2 23 16 3 15 8 4 7 0 12 34 56 78 1 31 0 12345678 Big Big 16 8 1 31 24 2 23 16 3 15 8 4 7 0 12 34 56 78 1 31 24 2 23 16 3 15 8 4 7 0 12121212 34343434 56565656 78787878 Big Big 16 16 1...

Page 717: ...to access the bus It is recommended that memory to memory transactions use the low priority channel Otherwise other lower priority AHB bus masters are prevented from accessing the bus during GPDMA mem...

Page 718: ...stated in the relevant text Unless otherwise stated in the relevant text all registers support read and write accesses A write updates the contents of a register and a read returns the contents of the...

Page 719: ...onfiguration Registers DMACC0Configuration 0xFFE0 4110 and DMACC1Configuration 0xFFE0 4130 This causes any further DMA requests to be ignored 2 Poll the Active bit in the relevant channel Configuratio...

Page 720: ...he DMACCxLLI Register Section 32 6 2 3 Channel Linked List Item Registers DMACC0LLI 0xFFE0 4108 and DMACC1LLI 0xFFE0 4128 If the transfer consists of a single packet of data then 0 must be written int...

Page 721: ...CSoftLBReq Software Last Burst Request Register R W 0x0000 0xFFE0 4028 DMACSoftLSReq Software Last Single Request Register R W 0x0000 0xFFE0 402C DMACConfiguration Configuration Register R W 0x0000 00...

Page 722: ...assignments of the DMACIntErrorStatus Register Table 654 Interrupt Status register DMACIntStatus address 0xFFE0 4000 bit description Bit Symbol Description Reset Value 0 IntStatus0 Status of channel...

Page 723: ...bit indicates that the error interrupt request is active prior to masking Table 32 660 shows the bit assignments of register of the DMACRawIntErrorStatus Register Table 657 Interrupt Error Status regi...

Page 724: ...d at the same time Table 660 Raw Error Interrupt Status register DMACRawIntErrorStatus address 0xFFE0 4018 bit description Bit Symbol Description Reset Value 0 RawIntErrorStatus0 Status of the error i...

Page 725: ...12 Software Last Single Request Register DMACSoftLSReq 0xFFE0 402C The DMACSoftLSReq Register is read write and enables DMA last single requests to be generated by software A DMA request can be genera...

Page 726: ...st register DMACSoftLSReq address 0xFFE0 402C bit description Bit Symbol Description Reset Value 3 0 Reserved user software should not write ones to reserved bits The value read from a reserved bit is...

Page 727: ...d It is intended to be read only when the channel has stopped in which case it shows the source address of the last item read Note The source and destination addresses must be aligned to the source an...

Page 728: ...such as the transfer size burst size and transfer width Each register is programmed directly by software before the DMA channel is enabled When the channel is enabled the register is updated by follow...

Page 729: ...ive in the source peripheral 0 17 15 DBsize Destination burst size Indicates the number of transfers that make up a destination burst transfer request This value must be set to the burst size of the d...

Page 730: ...8 111 256 Table 673 Source or destination transfer width Bit value of DBWidth or SBWidth Source or distention burst transfer request size 000 Byte 8 bit 001 Halfword 16 bit 010 Word 32 bit 011 and 1xx...

Page 731: ...ntrol Bit Value Description Reset Value Table 675 Channel Configuration registers DMACC0Configuration address 0xFFE0 4110 and DMACC1Configuration address 0xFFE0 4130 bit description Bit Symbol Value D...

Page 732: ...See the SrcPeripheral symbol description for values 0 10 Reserved do not modify masked on read NA 13 11 FlowCntrl Flow control and transfer type This value indicates the flow controller and transfer t...

Page 733: ...t to 0 The source and destination data areas are defined by a series of linked lists Each Linked List Item LLI controls the transfer of one block of data and then optionally loads another LLI to conti...

Page 734: ...on information to the channel Configuration Register and set the Channel Enable bit The GPDMA then transfers the first and then subsequent packets of data as each linked list item is loaded 5 An inter...

Page 735: ...ransfer width word 32 bit Transfer size 3 072 bytes 0xC00 Source and destination burst sizes 16 transfers Next LLI address 0x0 Because the next LLI address is set to zero this is the last descriptor a...

Page 736: ...rrupt request 9 2 Interrupt polling sequence flow Used when the GPDMA interrupt request signal is either masked out disabled in the interrupt controller or disabled in the processor When polling the G...

Page 737: ...MA responds with a DMA acknowledge The terminal count interrupt is generated this interrupt can be masked If the DMACCxLLI Register is not 0 then reload the DMACCxSrcAddr DMACCxDestAddr DMACCxLLI and...

Page 738: ...peripheral is performing flow control The following happens The GPDMA responds with a DMA acknowledge to the destination peripheral The terminal count interrupt is generated this interrupt can be mas...

Page 739: ...ource or destination peripherals can be used as the flow controller For simple or low performance peripherals that know the packet length that is when the peripheral is the flow controller a simple wa...

Page 740: ...AG style scan chains within the ARM7TDMI S A JTAG style Test Access Port Controller controls the scan chains In addition to the scan chains the debug architecture uses EmbeddedICE logic which resides...

Page 741: ...r to IEEE Standard 1149 1 1990 Standard Test Access Port and Boundary Scan Architecture 4 Pin description 1 This pin has a built in pull up resistor 2 This pin has no built in pull up and no built in...

Page 742: ...c registers Name Width Description Address Debug Control 6 Force debug state disable interrupts 00000 Debug Status 5 Status of debug 00001 Debug Comms Control Register 32 Debug communication control r...

Page 743: ...mber 2008 743 of 792 NXP Semiconductors UM10237 Chapter 33 LPC24XX EmbeddedICE Fig 147 EmbeddedICE debug environment block diagram ARM7TDMI S TARGET BOARD EMBEDDED ICE INTERFACE PROTOCOL CONVERTER EMB...

Page 744: ...through a narrow trace port An external Trace Port Analyzer captures the trace information under software debugger control Trace port can broadcast the Instruction trace information Instruction trace...

Page 745: ...cient hold time for the trace data signals Half rate clocking mode is supported Trace data signals should be shifted by a clock phase from TRACECLK Refer to Figure 3 14 page 3 26 and figure 3 15 page...

Page 746: ...ess of the comparison WO 000 0111 Trace Enable Event Holds the enabling event WO 000 1000 Trace Enable Control 1 Holds the include and exclude regions WO 000 1001 FIFOFULL Region Holds the include and...

Page 747: ...Embedded Trace Module ETM 7 Block diagram The block diagram of the ETM debug environment is shown below in Figure 34 148 Fig 148 ETM debug environment block diagram PERIPHERAL TRACE PORT ANALYZER TRAC...

Page 748: ...r Multi ICE or other JTAG unit and EmbeddedICE logic a hardware based debug solution Although both of these methods provide robust debugging environments neither is suitable as a lightweight real time...

Page 749: ...nit The RMHost controller RealMonitor dll converts generic Remote Debug Interface RDI requests from the debugger into DCC only RDI messages for the JTAG unit For complete details on debugging a RealMo...

Page 750: ...t component RMHost using the Debug Communications Channel DCC which is a reliable link whose data is carried over the JTAG connection While user application is running RMTarget typically uses IRQs gen...

Page 751: ...ion Both IRQs and FIQs continue to be serviced if they were enabled by the application at the time the foreground application was stopped 4 How to enable RealMonitor The following steps must be perfor...

Page 752: ...eptions Figure 35 151 illustrates how exceptions can be claimed by RealMonitor itself or shared between RealMonitor and application If user application requires the exception sharing they must provide...

Page 753: ...ORT rm_prefetchabort_handler IMPORT rm_dataabort_handler IMPORT rm_irqhandler2 IMPORT rm_undef_handler IMPORT User_Entry Entry point of user application CODE32 ENTRY Define exception table Instruct li...

Page 754: ..._end EQU 0x4000xxxx Top of on chip RAM __init Set up the stack pointers for various processor modes Stack grows downwards LDR r2 ram_end Get top of RAM MRS r0 CPSR Save current processor mode Initiali...

Page 755: ...or MRS r1 CPSR get the CPSR BIC r1 r1 0xC0 enable IRQs and FIQs MSR CPSR_c r1 update the CPSR Get the address of the User entry point LDR lr User_Entry MOV pc lr Non vectored irq handler app_irqDispat...

Page 756: ...et to host packets sent on a non RealMonitor third party channel RM_OPT_STOPSTART TRUE This option enables or disables support for all stop and start debugging features RM_OPT_SOFTBREAKPOINT TRUE This...

Page 757: ...code buffer size Also refer to RM_OPT_EXECUTECODE option RM_OPT_GATHER_STATISTICS FALSE This option enables or disables the code for gathering statistics about the internal operation of RealMonitor RM...

Page 758: ...December 2008 758 of 792 NXP Semiconductors UM10237 Chapter 35 LPC24XX RealMonitor This option specifies the size in words of the data logging FIFO buffer CHAIN_VECTORS FALSE This option allows RMTarg...

Page 759: ...Detection CAN Controller Area Network DAC Digital to Analog Converter DCC Debug Communication Channel DMA Direct Memory Access DSP Digital Signal Processing EOP End Of Packet ETM Embedded Trace Macroc...

Page 760: ...specifications and product descriptions at any time and without notice This document supersedes and replaces all information supplied prior to the publication hereof Suitability for use NXP Semiconduc...

Page 761: ...l and external components parameters low frequency mode OSCRANGE 0 see Table 3 29 44 Table 40 Recommended values for CX1 X2 in oscillation mode crystal and external components parameters high frequenc...

Page 762: ...ters EMCStaticWaitOen03 address 0xFFE0 8208 0xFFE0 8228 0xFFE0 8248 0xFFE0 8268 bit description 93 Table 92 Static Memory Read Delay registers EMCStaticWaitRd0 3 address 0xFFE0 820C 0xFFE0 822C 0xFFE0...

Page 763: ...s 0xE002 C040 bit description 189 Table 147 Pin Mode select register 1 PINMODE1 address 0xE002 C044 bit description 190 Table 148 Pin Mode select register 2 PINMODE2 address 0xE002 C048 bit descriptio...

Page 764: ...le 201 MII Mgmt Read Data register MRDD address 0xFFE0 0030 bit description 225 Table 202 MII Mgmt Indicators register MIND address 0xFFE0 0034 bit description 226 Table 203 Station Address register S...

Page 765: ...xFFE1 0008 306 Table 264 Line End Control register LCD_LE RW 0xFFE1 000C 309 Table 265 Upper Panel Frame Base register LCD_UPBASE RW 0xFFE1 0010 309 Table 266 Lower Panel Frame Base register LCD_LPBAS...

Page 766: ...egister USBEpIn address 0xFFE0 C248 bit description 348 Table 320 USB MaxPacketSize register USBMaxPSize address 0xFFE0 C24C bit description 348 Table 321 USB Receive Data register USBRxData address 0...

Page 767: ...cription 422 Table 377 UART Register Map 424 Table 378 UARTn Receiver Buffer Register U0RBR address 0xE000 C000 U2RBR 0xE007 8000 U3RBR 0E007 C000 when DLAB 0 Read Only bit description 426 Table 379 U...

Page 768: ...8 CAN2EWL address 0xE004 8018 bit description 487 Table 427 Status Register CAN1SR address 0xE004 401C CAN2SR address 0xE004 801C bit description 487 Table 428 Receive Frame Status register CAN1RFS ad...

Page 769: ...MIS address 0xE006 801C SSP1MIS 0xE003 001C bit description 550 Table 479 SSPn interrupt Clear Register SSP0ICR address 0xE006 8020 SSP1ICR 0xE003 0020 bit description 550 Table 480 SSPn DMA Control R...

Page 770: ...level comparison 619 Table 543 DMA and interrupt request generation 619 Table 544 Status feedback in the I2SSTATE register 619 Table 545 Timer Counter pin description 622 Table 546 Summary of timer co...

Page 771: ...Read Protection options 682 Table 603 Code Read Protection hardware software interaction 683 Table 604 ISP command summary 683 Table 605 ISP Unlock command 684 Table 606 ISP Set Baud Rate command 684...

Page 772: ...description 726 Table 666 Configuration register DMACConfiguration address 0xFFE0 4030 bit description 726 Table 667 Synchronization register DMACSync address 0xFFE0 4034 bit description 726 Table 668...

Page 773: ...or TFT displays 324 Fig 45 USB device controller block diagram 331 Fig 46 USB MaxPacketSize register array indexing 349 Fig 47 Interrupt event handling 361 Fig 48 UDCA Head register and DMA Descriptor...

Page 774: ...to master Transmitter after sending repeated START 576 Fig 115 Format of Slave Receiver mode 576 Fig 116 Format of Slave Transmitter mode 577 Fig 117 I2C Bus serial interface block diagram 578 Fig 11...

Page 775: ...description 29 3 1 2 External Interrupt flag register EXTINT 0xE01F C140 29 3 1 3 External Interrupt Mode register EXTMODE 0xE01F C148 31 3 1 4 External Interrupt Polarity register EXTPOLAR 0xE01F C1...

Page 776: ...10 4 Dynamic Memory Control register EMCDynamicControl 0xFFE0 8020 78 10 5 Dynamic Memory Refresh Timer register EMCDynamicRefresh 0xFFE0 8024 80 10 6 Dynamic Memory Read Configuration register EMCDyn...

Page 777: ...upt Enable Clear Register VICIntEnClear 0xFFFF F014 112 3 6 Interrupt Select Register VICIntSelect 0xFFFF F00C 112 3 7 IRQ Status Register VICIRQStatus 0xFFFF F000 113 3 8 FIQ Status Register VICFIQSt...

Page 778: ...IN 0xE002 80 0 1 0 and FIO 0 1 2 3 4 PIN 0x3FFF C0 1 3 5 7 9 4 202 6 5 Fast GPIO port Mask register FIOMASK FIO 0 1 2 3 4 MASK 0x3FFF C0 1 3 5 7 9 0 204 6 6 GPIO interrupt registers 206 6 6 1 GPIO ove...

Page 779: ...0 0160 233 7 2 16 Flow Control Counter Register FlowControlCounter 0xFFE0 0170 234 7 2 17 Flow Control Status Register FlowControlStatus 0xFFE0 0174 235 7 3 Receive filter register definitions 235 7 3...

Page 780: ...ontrol register LCD_LE RW 0xFFE1 000C 308 7 6 Upper Panel Frame Base Address register LCD_UPBASE RW 0xFFE1 0010 309 7 7 Lower Panel Frame Base Address register LCD_LPBASE RW 0xFFE1 0014 309 7 8 LCD Co...

Page 781: ...cket Length register USBRxPLen 0xFFE0 C220 349 9 6 3 USB Transmit Data register USBTxData 0xFFE0 C21C 350 9 6 4 USB Transmit Packet Length register USBTxPLen 0xFFE0 C224 350 9 6 5 USB Control register...

Page 782: ...e_memory_address 378 14 5 Non isochronous endpoint operation 378 14 5 1 Setting up DMA transfers 378 14 5 2 Finding DMA Descriptor 378 14 5 3 Transferring the data 379 14 5 4 Optimizing descriptor fet...

Page 783: ...er description 423 16 4 1 UARTn Receiver Buffer Register U0RBR 0xE000 C000 U2RBR 0xE007 8000 U3RBR 0xE007 C000 when DLAB 0 Read Only 426 4 2 UARTn Transmit Holding Register U0THR 0xE000 C000 U2THR 0xE...

Page 784: ...nterface Management Logic IML 469 6 3 Transmit Buffers TXB 470 6 4 Receive Buffer RXB 470 6 5 Error Management Logic EML 471 6 6 Bit Timing Logic BTL 471 6 7 Bit Stream Processor BSP 471 6 8 CAN contr...

Page 785: ...s IntPnd 63 to 0 513 17 2 4 Clearing the interrupt pending bits IntPnd 63 to 0 513 17 2 5 Setting the message lost bit of a FullCAN message object MsgLost 63 to 0 513 17 2 6 Clearing the message lost...

Page 786: ...Masked Interrupt Status Register SSP0MIS 0xE006 801C SSP1MIS 0xE003 001C 549 6 9 SSPn Interrupt Clear Register SSP0ICR 0xE006 8020 SSP1ICR 0xE003 0020 550 6 10 SSPn DMA Control Register SSP0DMACR 0xE...

Page 787: ...8 8 Selecting the appropriate I2C data rate and duty cycle 585 9 Details of I2C operating modes 586 9 1 Master Transmitter mode 587 9 2 Master Receiver mode 588 9 3 Slave Receiver mode 588 9 4 Slave...

Page 788: ...08 626 6 5 Prescale register T0PR T3PR 0xE000 400C 0xE000 800C 0xE007 000C 0xE007 400C 626 6 6 Prescale Counter register T0PC T3PC 0xE000 4010 0xE000 8010 0xE007 0010 0xE007 4010 626 6 7 Match Registe...

Page 789: ...24XX WatchDog Timer WDT 1 Features 662 2 Applications 662 3 Description 662 4 Register description 663 4 1 Watchdog Mode Register WDMOD 0xE000 0000 663 4 2 Watchdog Timer Constant Register WDTC 0xE000...

Page 790: ...er 697 2 Features 697 3 Applications 697 4 Description 697 4 1 Memory map after any reset 698 4 2 Communication protocol 698 4 2 1 ISP command format 699 4 2 2 ISP response format 699 4 2 3 ISP data f...

Page 791: ...figuration 0xFFE0 4030 726 6 1 14 Synchronization Register DMACSync 0xFFE0 4034 726 6 2 Channel registers 727 6 2 1 Channel Source Address Registers DMACC0SrcAddr 0xFFE0 4100 and DMACC1SrcAddr 0xFFE0...

Page 792: ...information 792 3 1 1 RMHost 749 3 1 2 RMTarget 749 3 2 How RealMonitor works 750 4 How to enable RealMonitor 751 4 1 Adding stacks 751 4 2 IRQ mode 751 4 3 Undef mode 751 4 4 SVC mode 751 4 5 Prefetc...

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Summary of Contents for LPC24XX UM10237

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Summary of Contents for LPC24XX UM10237

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