NXP Semiconductors LPC1751, User Manual, Page: 732 / 808

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UM10360_0 © NXP B.V. 2009. All rights reserved.
User manual Rev. 00.06 — 5 June 2009 732 of 808
NXP Semiconductors
UM10360
Chapter 34: Appendix: Cortex-M3 User Guide
4.2.4 Interrupt Set-pending Registers
The ISPR0-ISPR3 registers force interrupts into the pending state, and show which
interrupts are pending. See:
•
the register summary in Table 34–616 for the register attributes
•
Table 34–617 for which interrupts are controlled by each register.
The bit assignments are shown in Table 34–620 .
Remark: Writing 1 to the ISPR bit corresponding to:
•
an interrupt that is pending has no effect
•
a disabled interrupt sets the state of that interrupt to pending.
4.2.5 Interrupt Clear-pending Registers
The ICPR0-ICPR3 registers remove the pending state from interrupts, and show which
interrupts are pending. See:
•
the register summary in Table 34–616 for the register attributes
•
Table 34–617 for which interrupts are controlled by each register.
The bit assignments are shown in Table 34–621 .
Table 619. ICER bit assignments
Bits Name Function
[31:0] CLRENA Interrupt clear-enable bits.
Write:
0 = no effect
1 = disable interrupt.
Read:
0 = interrupt disabled
1 = interrupt enabled.
Table 620. ISPR bit assignments
Bits Name Function
[31:0] SETPEND Interrupt set-pending bits.
Write:
0 = no effect
1 = changes interrupt state to pending.
Read:
0 = interrupt is not pending
1 = interrupt is pending.