NXP Semiconductors LPC1751, User Manual, Page: 730 / 808

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UM10360_0 © NXP B.V. 2009. All rights reserved.
User manual Rev. 00.06 — 5 June 2009 730 of 808
NXP Semiconductors
UM10360
Chapter 34: Appendix: Cortex-M3 User Guide
4.2 Nested Vectored Interrupt Controller
This section describes the Nested Vectored Interrupt Controller (NVIC) and the registers it
uses. The NVIC supports:
•
Up to 112 interrupts. The number of interrupts implemented is device dependent.
•
A programmable priority level of 0 to 31 for each interrupt. A higher level corresponds
to a lower priority, so level 0 is the highest interrupt priority.
•
Level and pulse detection of interrupt signals.
•
Dynamic reprioritization of interrupts.
•
Grouping of priority values into group priority and subpriority fields.
•
Interrupt tail-chaining.
•
An external Non-maskable interrupt (NMI).
The processor automatically stacks its state on exception entry and unstacks this state on
exception exit, with no instruction overhead. This provides low latency exception handling.
The hardware implementation of the NVIC registers is:
[1] Each array element corresponds to a single NVIC register, for example the element ICER[1] corresponds to the ICER1 register.
4.2.1 The CMSIS mapping of the Cortex-M3 NVIC registers
To improve software efficiency, the CMSIS simplifies the NVIC register presentation. In the
CMSIS:
•
the Set-enable, Clear-enable, Set-pending, Clear-pending and Active Bit registers
map to arrays of 32-bit integers, so that:
– the array
ISER[0]
to
ISER[3]
corresponds to the registers ISER0 - ISER3
– the array
ICER[0]
to
ICER[3]
corresponds to the registers ICER0 - ICER3
– the array
ISPR[0]
to
ISPR[3]
corresponds to the registers ISPR0 - ISPR3
– the array
ICPR[0]
to
ICPR[3]
corresponds to the registers ICPR0 - ICPR3
– the array
IABR[0]
to
IABR[3]
corresponds to the registers IABR0 - IABR3.
•
the 8-bit fields of the Interrupt Priority Registers map to an array of 8-bit integers, so
that the array
IP[0]
to
IP[112]
corresponds to the registers IPR0 - IPR59, and the
array entry
IP[n]
holds the interrupt priority for interrupt n .
Table 616. NVIC register summary
Address Name Type Required
privilege Reset
value Description
0xE000E100
-
0xE000E11C
ISER0 - ISER3 RW Privileged
0x00000000
Table 34–618
0XE000E180
-
0xE000E19C
ICER0 - ICER3 RW Privileged
0x00000000
Table 34–619
0XE000E200
-
0xE000E21C
ISPR0 - ISPR3 RW Privileged
0x00000000
Table 34–620
0XE000E280
-
0xE000E29C
ICPR0 - ICPR3 RW Privileged
0x00000000
Table 34–621
0xE000E300
-
0xE000E31C
IABR0 - IABR3 RO Privileged
0x00000000
Table 34–622
0xE000E400
-
0xE000E46F
IPR0 - IPR27 RW Privileged
0x00000000
Table 34–623
0xE000EF00
STIR WO Configurable
[1]
0x00000000
Table 34–624