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UM10360_0
© NXP B.V. 2009. All rights reserved.
User manual
Rev. 00.06 — 5 June 2009
572 of 808
NXP Semiconductors
UM10360
Chapter 31: LPC17xx General Purpose DMA (GPDMA) controller
5.9 DMA Software Burst Request register (DMACSoftBReq - 0x5000 4020)
The DMACSoftBReq Register is read/write and enables DMA burst requests to be
generated by software. A DMA request can be generated for each source by writing a 1 to
the corresponding register bit. A register bit is cleared when the transaction has
completed. Reading the register indicates which sources are requesting DMA burst
transfers. A request can be generated from either a peripheral or the software request
register. Each bit is cleared when the related transaction has completed.
shows the bit assignments of the DMACSoftBReq Register.
Note:
It is recommended that software and hardware peripheral requests are not used at
the same time.
5.10 DMA Software Single Request register (DMACSoftSReq - 0x5000
4024)
The DMACSoftSReq Register is read/write and enables DMA single transfer requests to
be generated by software. A DMA request can be generated for each source by writing a
1 to the corresponding register bit. A register bit is cleared when the transaction has
completed. Reading the register indicates which sources are requesting single DMA
transfers. A request can be generated from either a peripheral or the software request
register.
shows the bit assignments of the DMACSoftSReq Register.
Table 534. DMA Enabled Channel register (DMACEnbldChns - 0x5000 401C)
Bit
Name
Function
7:0
EnabledChannels
Enable status for DMA channels. Each bit represents one channel:
0 - DMA channel is disabled.
1 - DMA channel is enabled.
31:8
-
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Table 535. DMA Software Burst Request register (DMACSoftBReq - 0x5000 4020)
Bit
Name
Function
15:0
SoftBReq
Software burst request flags for each of 16 possible sources. Each bit represents one
DMA request line or peripheral function (refer to
for peripheral
hardware connections to the DMA controller):
0 - writing 0 has no effect.
1 - writing 1 generates a DMA burst request for the corresponding request line.
31:16
-
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Table 536. DMA Software Single Request register (DMACSoftSReq - 0x5000 4024)
Bit
Name
Function
15:0
SoftSReq
Software single transfer request flags for each of 16 possible sources. Each bit
represents one DMA request line or peripheral function:
0 - writing 0 has no effect.
1 - writing 1 generates a DMA single transfer request for the corresponding request
line.
31:16
-
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.