NXP Semiconductors LPC1751, User Manual, Page: 567 / 808

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UM10360_0 © NXP B.V. 2009. All rights reserved.
User manual Rev. 00.06 — 5 June 2009 567 of 808
NXP Semiconductors
UM10360
Chapter 31: LPC17xx General Purpose DMA (GPDMA) controller
4.2.3 DMA request connections
The connection of the GPDMA to the supported peripheral devices depends on the DMA
functions implemented in those peripherals.
Table 31–525 shows the DMA Request
numbers used by the supported peripherals. UART and timer DMA requests on channels
8 through 15 are chosen via the DMAREQSEL register, see
Section 31–5.15 .
5. Register description
The DMA Controller supports 8 channels. Each channel has registers specific to the
operation of that channel. Other registers controls aspects of how source peripherals
relate to the DMA Controller. There are also global DMA control and status registers.
The DMA Controller registers are shown in Table 31–526 .
Table 525. DMA Connections
Peripheral Function DMA Single
Request Input
(DMACSREQ) DMA Burst
Request Input
(DMACBREQ)
SSP0 Tx 0 0
SSP0 Rx 1 1
SSP1 Tx 2 2
SSP1 Rx 3 3
ADC 4 4
I
2
S channel 0 - 5
I
2
S channel 1 - 6
DAC - 7
UART0 Tx / MAT0.0 - 8
UART0 Rx / MAT0.1 - 9
UART1 Tx / MAT1.0 - 10
UART1 Rx / MAT1.1 - 11
UART2 Tx / MAT2.0 - 12
UART2 Rx / MAT2.1 - 13
UART3 Tx / MAT3.0 - 14
UART3 Rx / MAT3.1 - 15
Table 526. GPDMA register map
Name Description Reset state Access Address
General registers
DMACIntStat DMA Interrupt Status Register 0 RO 0x5000 4000
DMACIntTCStat DMA Interrupt Terminal Count Request Status
Register 0 RO 0x5000 4004
DMACIntTCClear DMA Interrupt Terminal Count Request Clear
Register - WO 0x5000 4008
DMACIntErrStat DMA Interrupt Error Status Register 0 RO 0x5000 400C
DMACIntErrClr DMA Interrupt Error Clear Register - WO 0x5000 4010
DMACRawIntTCStat DMA Raw Interrupt Terminal Count Status Register 0 RO 0x5000 4014