NXP Semiconductors LPC1751, User Manual, Page: 550 / 808

DR
AFT
DR
AFT
DRAFT
DR
D
RAFT
DRAFT
DRA
FT DRAF
D
RAFT DRAFT DRAFT DRAFT DRAFT D
DRAFT
D
RAFT DRA
FT DRAFT DRAFT DRAFT DRA
UM10360_0 © NXP B.V. 2009. All rights reserved.
User manual Rev. 00.06 — 5 June 2009 550 of 808
NXP Semiconductors
UM10360
Chapter 29: LPC17xx Analog-to-Digital Converter (ADC)
5. Register description
The A/D Converter registers are shown in Table 29–512 .
Table 511. ADC pin description
Pin Type Description
AD0.7 to AD0.0 Input Analog Inputs. The ADC cell can measure the voltage on any of these input signals.
Note that these analog inputs are always connected to their pins, even if the Pin
function Select register assigns them to port pins. A simple self-test of the ADC can be
done by driving these pins as port outputs.
Note: if the ADC is used, signal levels on analog input pins must not be above the
level of V
DDA
at any time. Otherwise, A/D converter readings will be invalid. If the A/D
converter is not used in an application then the pins associated with A/D inputs can be
used as 5 V tolerant digital IO pins.
Warning: while the ADC pins are specified as 5 V tolerant ( Table 7–51 ), the analog
multiplexing in the ADC block is not. More than 3.3 V (V
DDA
) should not be applied to
any pin that is selected as an ADC input, or the ADC reading will be incorrect. If for
example AD0.0 and AD0.1 are used as the ADC0 inputs and voltage on AD0.0 = 4.5 V
while AD0.1 = 2.5 V, an excessive voltage on the AD0.0 can cause an incorrect
reading of the AD0.1, although the AD0.1 input voltage is within the right range.
V
REF
Reference Voltage Reference. This pin is provides a voltage reference level for the ADC and
DAC. Note: this pin should be tied to V
DD(3V3)
if the ADC and DAC are not used.
V
DDA
, V
SSA
Power Analog Power and Ground. These should be nominally the same voltages as V
DD
and V
SS
, but should be isolated to minimize noise and error. Note: this pin should be
tied to V
DD(3V3)
if the ADC and DAC are not used.
Table 512. ADC registers
Generic
Name Description Access Reset value
[1]
AD0
Address
& Name
ADCR A/D Control Register. The ADCR register must be written to
select the operating mode before A/D conversion can occur. R/W 0x0000 0001 0x4003 4000
AD0CR
ADGDR A/D Global Data Register. This register contains the ADC’s
DONE bit and the result of the most recent A/D conversion. R/W NA 0x4003 4004
AD0GDR
ADINTEN A/D Interrupt Enable Register. This register contains enable bits
that allow the DONE flag of each A/D channel to be included or
excluded from contributing to the generation of an A/D interrupt. R/W 0x0000 0100 0x4003 400C
AD0INTEN
ADDR0 A/D Channel 0 Data Register. This register contains the result of
the most recent conversion completed on channel 0. RO NA 0x4003 4010
AD0DR0
ADDR1 A/D Channel 1 Data Register. This register contains the result of
the most recent conversion completed on channel 1. RO NA 0x4003 4014
AD0DR1
ADDR2 A/D Channel 2 Data Register. This register contains the result of
the most recent conversion completed on channel 2. RO NA 0x4003 4018
AD0DR2
ADDR3 A/D Channel 3 Data Register. This register contains the result of
the most recent conversion completed on channel 3. RO NA 0x4003 401C
AD0DR3
ADDR4 A/D Channel 4 Data Register. This register contains the result of
the most recent conversion completed on channel 4. RO NA 0x4003 4020
AD0DR4
ADDR5 A/D Channel 5 Data Register. This register contains the result of
the most recent conversion completed on channel 5. RO NA 0x4003 4024
AD0DR5
ADDR6 A/D Channel 6 Data Register. This register contains the result of
the most recent conversion completed on channel 6. RO NA 0x4003 4028
AD0DR6