NXP Semiconductors LPC1102, User Manual

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User manual Rev. 1 — 20 October 2010 37 of 258
NXP Semiconductors
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Chapter 3: LPC1102 System configuration
1. Specify the input clock frequency FCLKIN.
2. Calculate M to obtain the desired output frequency FCLKOUT with
M = FCLKOUT / FCLKIN.
3. Find a value so that FCCO = 2
×
P
×
FCLKOUT.
4. Verify that all frequencies and divider values conform to the limits specified in Table 8 .
5. Ensure that FCLKOUT < 100 MHz.
Table 38 shows how to configure the PLL for a 12 MHz crystal oscillator using the
SYSPLLCTRL register ( Table 8 ). The main clock is equivalent to the system clock if the
system clock divider SYSAHBCLKDIV is set to one (see Table 18 ).
3.10.4.2 Power-down mode
In this mode, the internal current reference will be turned off, the oscillator and the
phase-frequency detector will be stopped and the dividers will enter a reset state. While in
Power-down mode, the lock output will be low, to indicate that the PLL is not in lock. When
the Power-down mode is terminated by setting the SYSPLL_PD bit to zero in the
Power-down configuration register (
Table 35 ), the PLL will resume its normal operation
and will make the lock signal HIGH once it has regained lock on the input clock.
3.11 Flash memory access
Depending on the system clock frequency, access to the flash memory can be configured
with various access times by writing to the FLASHCFG register at address 0x4003 C010.
This register is part of the flash configuration block (see
Figure 2 ).
Remark: Improper setting of this register may result in incorrect operation of the LPC1102
flash memory.
Table 38. PLL configuration examples
PLL input
clock
sys_pllclkin
(FCLKIN) Main clock
(FCLKOUT) MSEL bits
Table 8
M divider
value PSEL bits
Table 8
P divider
value FCCO
frequency
12 MHz 48 MHz 00011 4 01 2 192 MHz
12 MHz 36 MHz 00010 3 10 4 288 MHz
12 MHz 24 MHz 00001 2 10 4 192 MHz