UM10429
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User manual
Rev. 1 — 20 October 2010
30 of 258
NXP Semiconductors
UM10429
Chapter 3: LPC1102 System configuration
3.6 Reset
Reset has four sources on the LPC1102: the RESET pin, Watchdog Reset, Power-On
Reset (POR), and Brown Out Detect (BOD). In addition, there is a software reset.
The RESET pin is a Schmitt trigger input pin. Assertion of chip Reset by any source, once
the operating voltage attains a usable level, starts the IRC causing reset to remain
asserted until the external Reset is de-asserted, the oscillator is running, and the flash
controller has completed its initialization.
On the assertion of a reset source external to the Cortex-M0 CPU (POR, BOD reset,
External reset, and Watchdog reset), the following processes are initiated:
1. The IRC starts up. After the IRC-start-up time (maximum of 6
μ
s on power-up), the
IRC provides a stable clock output.
2. The boot code in the ROM starts. The boot code performs the boot tasks and may
jump to the flash.
3. The flash is powered up. This takes approximately 100
μ
s. Then the flash initialization
sequence is started, which takes about 250 cycles.
When the internal Reset is removed, the processor begins executing at address 0, which
is initially the Reset vector mapped from the boot block. At that point, all of the processor
and peripheral registers have been initialized to predetermined values.
3.7 Brown-out detection
The LPC1102 includes four levels for monitoring the voltage on the V
DD
pin. If this voltage
falls below one of the four selected levels, the BOD asserts an interrupt signal to the
NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC
in order to cause a CPU interrupt; if not, software can monitor the signal by reading the
NVIC status register (see
). An additional four threshold levels can be selected to
cause a forced reset of the chip (see
).
3.8 Power management
The LPC1102 support a variety of power control features. In Active mode, when the chip
is running, power and clocks to selected peripherals can be optimized for power
consumption. In addition, there are three special modes of processor power reduction:
Sleep mode and Deep-sleep mode mode.
Remark:
The Debug mode is not supported in Sleep or Deep-sleep mode.
3.8.1 Active mode
In Active mode, the ARM Cortex-M0 core and memories are clocked by the system clock,
and peripherals are clocked by the system clock or a dedicated peripheral clock.
The chip is in Active mode after reset and the default power configuration is determined
by the reset values of the PDRUNCFG and SYSAHBCLKCTRL registers. The power
configuration can be changed during run time.
