NXP Semiconductors LPC1102, User Manual

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User manual Rev. 1 — 20 October 2010 209 of 258
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Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference
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The exception is LR for a PUSH and PC for a POP.
19.4.4.6.4 Condition flags
These instructions do not change the flags.
19.4.4.6.5 Examples
PUSH {R0,R4-R7} ; Push R0,R4,R5,R6,R7 onto the stack
PUSH {R2,LR} ; Push R2 and the link-register onto the stack
POP {R0,R6,PC} ; Pop r0,r6 and PC from the stack, then branch to
; the new PC.
19.4.5 General data processing instructions
Table 207 shows the data processing instructions:
Table 207. Data processing instructions
Mnemonic Brief description See
ADCS Add with Carry Section 19–19.4.5.1
ADD{S} Add Section 19–19.4.5.1
ANDS Logical AND Section 19–19.4.5.2
ASRS Arithmetic Shift Right Section 19–19.4.5.3
BICS Bit Clear Section 19–19.4.5.2
CMN Compare Negative Section 19–19.4.5.4
CMP Compare Section 19–19.4.5.4
EORS Exclusive OR Section 19–19.4.5.2
LSLS Logical Shift Left Section 19–19.4.5.3
LSRS Logical Shift Right Section 19–19.4.5.3
MOV{S} Move Section 19–19.4.5.5
MULS Multiply Section 19–19.4.5.6
MVNS Move NOT Section 19–19.4.5.5
ORRS Logical OR Section 19–19.4.5.2
REV Reverse byte order in a word Section 19–19.4.5.7
REV16 Reverse byte order in each halfword Section 19–19.4.5.7
REVSH Reverse byte order in bottom halfword
and sign extend Section 19–19.4.5.7
RORS Rotate Right Section 19–19.4.5.3
RSBS Reverse Subtract Section 19–19.4.5.1
SBCS Subtract with Carry Section 19–19.4.5.1
SUBS Subtract Section 19–19.4.5.1
SXTB Sign extend a byte Section 19–19.4.5.8
SXTH Sign extend a halfword Section 19–19.4.5.8
UXTB Zero extend a byte Section 19–19.4.5.8
UXTH Zero extend a halfword Section 19–19.4.5.8
TST Test Section 19–19.4.5.9