UM10429
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
User manual
Rev. 1 — 20 October 2010
210 of 258
NXP Semiconductors
UM10429
Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference
19.4.5.1 ADC, ADD, RSB, SBC, and SUB
Add with carry, Add, Reverse Subtract, Subtract with carry, and Subtract.
19.4.5.1.1
Syntax
ADCS {
Rd
,}
Rn
,
Rm
ADD{S} {
Rd
,}
Rn
,
<Rm|#imm>
RSBS {
Rd
,}
Rn
,
Rm
,
#0
SBCS {
Rd
,}
Rn
,
Rm
SUB{S} {
Rd
,}
Rn
,
<
Rm
|
#imm
>
Where:
S causes an ADD or SUB instruction to update flags
Rd
specifies the result register
Rn
specifies the first source register
Rm
specifies the second source register
imm
specifies a constant immediate value.
When the optional
Rd
register specifier is omitted, it is assumed to take the same value as
Rn
, for example ADDS R1,R2 is identical to ADDS R1,R1,R2.
19.4.5.1.2
Operation
The ADCS instruction adds the value in
Rn
to the value in
Rm
, adding a further one if the
carry flag is set, places the result in the register specified by
Rd
and updates the N, Z, C,
and V flags.
The ADD instruction adds the value in
Rn
to the value in
Rm
or an immediate value
specified by
imm
and places the result in the register specified by
Rd
.
The ADDS instruction performs the same operation as ADD and also updates the N, Z, C
and V flags.
The RSBS instruction subtracts the value in
Rn
from zero, producing the arithmetic
negative of the value, and places the result in the register specified by Rd and updates the
N, Z, C and V flags.
The SBCS instruction subtracts the value of
Rm
from the value in
Rn
, deducts a further
one if the carry flag is set. It places the result in the register specified by Rd and updates
the N, Z, C and V flags.
The SUB instruction subtracts the value in
Rm
or the immediate specified by
imm
. It
places the result in the register specified by
Rd
.
The SUBS instruction performs the same operation as SUB and also updates the N, Z, C
and V flags.
Use ADC and SBC to synthesize multiword arithmetic, see
.
