NXP Semiconductors LPC1102, User Manual

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User manual Rev. 1 — 20 October 2010 199 of 258
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Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference
Remark: When you update the PC with a BX, BLX, or POP instruction, bit[0] of any
address must be 1 for correct execution. This is because this bit indicates the destination
instruction set, and the Cortex-M0 processor only supports Thumb instructions. When a
BL or BLX instruction writes the value of bit[0] into the LR it is automatically assigned the
value 1.
19.4.3.3 Shift Operations
Register shift operations move the bits in a register left or right by a specified number of
bits, the
shift length . Register shift can be performed directly by the instructions ASR,
LSR, LSL, and ROR and the result is written to a destination register.The permitted shift
lengths depend on the shift type and the instruction, see the individual instruction
description. If the shift length is 0, no shift occurs. Register shift operations update the
carry flag except when the specified shift length is 0. The following sub-sections describe
the various shift operations and how they affect the carry flag. In these descriptions,
Rm is
the register containing the value to be shifted, and n is the shift length.
19.4.3.3.1 ASR
Arithmetic shift right by n bits moves the left-hand 32 - n bits of the register Rm , to the right
by n places, into the right-hand 32 - n bits of the result, and it copies the original bit[31] of
the register into the left-hand n bits of the result. See Figure 19–43 .
You can use the ASR operation to divide the signed value in the register Rm by 2
n
, with
the result being rounded towards negative-infinity.
When the instruction is ASRS the carry flag is updated to the last bit shifted out, bit[ n -1], of
the register Rm .
Remark:
•
If n is 32 or more, then all the bits in the result are set to the value of bit[31] of Rm .
•
If n is 32 or more and the carry flag is updated, it is updated to the value of bit[31] of
Rm .
19.4.3.3.2 LSR
Logical shift right by n bits moves the left-hand 32- n bits of the register Rm , to the right by
n places, into the right-hand 32 - n bits of the result, and it sets the left-hand n bits of the
result to 0. See Figure 44 .
Fig 43. ASR #3
31 1 0 2 4 5 3
...
Carry
Flag