NXP Semiconductors LPC1102, User Manual

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User manual Rev. 1 — 20 October 2010 196 of 258
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Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference
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angle brackets, <>, enclose alternative forms of the operand
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braces, {}, enclose optional operands and mnemonic parts
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the Operands column is not exhaustive.
For more information on the instructions and operands, see the instruction descriptions.
Table 202. Cortex-M0 instructions
Mnemonic Operands Brief description Flags Reference
ADCS {Rd,} Rn, Rm Add with Carry N,Z,C,V Section 19–19.4.5.1
ADD{S} {Rd,} Rn, <Rm|#imm> Add N,Z,C,V Section 19–19.4.5.1
ADR Rd, label PC-relative Address to Register - Section 19–19.4.4.1
ANDS {Rd,} Rn, Rm Bitwise AND N,Z Section 19–19.4.5.1
ASRS {Rd,} Rm, <Rs|#imm> Arithmetic Shift Right N,Z,C Section 19–19.4.5.3
B{cc} label Branch {conditionally} - Section 19–19.4.6.1
BICS {Rd,} Rn, Rm Bit Clear N,Z Section 19–19.4.5.2
BKPT #imm Breakpoint - Section 19–19.4.7.1
BL label Branch with Link - Section 19–19.4.6.1
BLX Rm Branch indirect with Link - Section 19–19.4.6.1
BX Rm Branch indirect - Section 19–19.4.6.1
CMN Rn, Rm Compare Negative N,Z,C,V Section 19–19.4.5.4
CMP Rn, <Rm|#imm> Compare N,Z,C,V Section 19–19.4.5.4
CPSID i Change Processor State, Disable
Interrupts - Section 19–19.4.7.2
CPSIE i Change Processor State, Enable
Interrupts - Section 19–19.4.7.2
DMB - Data Memory Barrier - Section 19–19.4.7.3
DSB - Data Synchronization Barrier - Section 19–19.4.7.4
EORS {Rd,} Rn, Rm Exclusive OR N,Z Section 19–19.4.5.2
ISB - Instruction Synchronization Barrier - Section 19–19.4.7.5
LDM Rn{!}, reglist Load Multiple registers, increment after - Section 19–19.4.4.5
LDR Rt, label Load Register from PC-relative address - Section 19–19.4.4
LDR Rt, [Rn, <Rm|#imm>] Load Register with word - Section 19–19.4.4
LDRB Rt, [Rn, <Rm|#imm>] Load Register with byte - Section 19–19.4.4
LDRH Rt, [Rn, <Rm|#imm>] Load Register with halfword - Section 19–19.4.4
LDRSB Rt, [Rn, <Rm|#imm>] Load Register with signed byte - Section 19–19.4.4
LDRSH Rt, [Rn, <Rm|#imm>] Load Register with signed halfword - Section 19–19.4.4
LSLS {Rd,} Rn, <Rs|#imm> Logical Shift Left N,Z,C Section 19–19.4.5.3
U {Rd,} Rn, <Rs|#imm> Logical Shift Right N,Z,C Section 19–19.4.5.3
MOV{S} Rd, Rm Move N,Z Section 19–19.4.5.5
MRS Rd, spec_reg Move to general register from special
register - Section 19–19.4.7.6
MSR spec_reg, Rm Move to special register from general
register N,Z,C,V Section 19–19.4.7.7
MULS Rd, Rn, Rm Multiply, 32-bit result N,Z Section 19–19.4.5.6
MVNS Rd, Rm Bitwise NOT N,Z Section 19–19.4.5.5