NXP Semiconductors LPC1102, User Manual

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User manual Rev. 1 — 20 October 2010 141 of 258
NXP Semiconductors
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Chapter 16: LPC1102 Analog-to-Digital Converter (ADC)
16.5 ADC clocking
Basic clocking for the A/D converters is determined by the APB clock (PCLK). A
programmable divider is included in the A/D converter to scale this clock to the 4.5 MHz
(max) clock needed by the successive approximation process. An accurate conversion
requires 11 clock cycles.
16.6 Register description
The ADC contains registers organized as shown in Table 140 .
[1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
16.6.1 A/D Control Register
The A/D Control Register provides bits to select A/D channels to be converted, A/D timing,
A/D modes, and the A/D start trigger.
Table 140. Register overview: ADC (base address 0x4001 C000)
Name Access Address
offset
Description Reset
Value
[1]
AD0CR R/W 0x000 A/D Control Register. The AD0CR register must be written to select the
operating mode before A/D conversion can occur. 0x0000 0000
AD0GDR R/W 0x004 A/D Global Data Register. Contains the result of the most recent A/D
conversion. NA
- - 0x008 Reserved. -
AD0INTEN R/W 0x00C A/D Interrupt Enable Register. This register contains enable bits that allow
the DONE flag of each A/D channel to be included or excluded from
contributing to the generation of an A/D interrupt. 0x0000 0100
AD0DR0 R/W 0x010 A/D Channel 0 Data Register. This register contains the result of the most
recent conversion completed on channel 0 NA
AD0DR1 R/W 0x014 A/D Channel 1 Data Register. This register contains the result of the most
recent conversion completed on channel 1. NA
AD0DR2 R/W 0x018 A/D Channel 2 Data Register. This register contains the result of the most
recent conversion completed on channel 2. NA
AD0DR3 R/W 0x01C A/D Channel 3 Data Register. This register contains the result of the most
recent conversion completed on channel 3. NA
AD0DR4 R/W 0x020 A/D Channel 4 Data Register. This register contains the result of the most
recent conversion completed on channel 4. NA
AD0DR5 R/W 0x024 Reserved. NA
AD0DR6 R/W 0x028 Reserved. NA
AD0DR7 R/W 0x02C Reserved. NA
AD0STAT RO 0x030 A/D Status Register. This register contains DONE and OVERRUN flags for
all of the A/D channels, as well as the A/D interrupt flag. 0