NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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Writing to the CNTIN register latches the value into a buffer. The CNTIN register is
updated with the value of its write buffer according to
Registers updated from write
buffers .
When the FTM clock is initially selected, by writing a non-zero value to the CLKS bits,
the FTM counter starts with the value 0x0000. To avoid this behavior, before the first
write to select the FTM clock, write the new value to the the CNTIN register and then
initialize the FTM counter by writing any value to the CNT register.
Address: Base a 4Ch offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
INIT
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FTMx_CNTIN field descriptions
Field Description
31–16
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
INIT Initial Value Of The FTM Counter
39.4.9 Capture And Compare Status (FTMx_STATUS)
The STATUS register contains a copy of the status flag CHF bit in CnSC for each FTM
channel for software convenience.
Each CHF bit in STATUS is a mirror of CHF bit in CnSC. All CHF bits can be checked
using only one read of STATUS. All CHF bits can be cleared by reading STATUS
followed by writing 0x00 to STATUS.
Hardware sets the individual channel flags when an event occurs on the channel. CHF is
cleared by reading STATUS while CHF is set and then writing a 0 to the CHF bit.
Writing a 1 to CHF has no effect.
If another event occurs between the read and write operations, the write operation has no
effect; therefore, CHF remains set indicating an event has occurred. In this case, a CHF
interrupt request is not lost due to the clearing sequence for a previous CHF.
Memory map and register definition
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
870 NXP Semiconductors