NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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ADCx_CFG2 field descriptions
Field Description
31–8
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
SMPLTS Sample Time Select
Selects a sample time of 2 to 256 ADCK clock cycles. The value written to this register field is the desired
sample time minus 1. A sample time of 1 is not supported. Allows higher impedance inputs to be
accurately sampled or conversion speed to be maximized for lower impedance inputs. Longer sample
times can also be used to lower overall power consumption when continuous conversions are enabled if
high conversion rates are not required.
36.4.4 ADC Data Result Registers (ADCx_Rn)
Rn contains the result of an ADC conversion of the channel selected by the
corresponding SC1A:SC1n. For every status and channel control register, there is a
corresponding data result register.
Unused bits in Rn are cleared.
The following table describes the behavior of the data result registers in the different
modes of operation.
Table 36-5. Data result register description
Conversion mode D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Format
12-bit single-ended D Unsigned right-
justified
10-bit single-ended 0 D
8-bit single-ended 0 D
D: Data. The data result registers are read-only; writing to these registers generates a
transfer error.
Address: Base a 48h (4d × i), where i=0d to 1d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0 D
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ADCx_Rn field descriptions
Field Description
31–12
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
D Data result
Chapter 36 Analog-to-Digital Converter (ADC)
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 747